Definition Of Programming/Erasure Times; Flash Memory Version Electrical Characteristics 10,000 E/W Cycle Products (U7, U9); Boot Mode; Standard Serial I/O Mode - Renesas M16C FAMILY series Hardware Manual

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20.14.14 Definition of Programming/Erasure Times

"Number of programs and erasure" refers to the number of erasure per block.
If the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times.
For example, if a 2K byte block A is erased after writing 1 word data 1024 times, each to a different
address, this is counted as one program and erasure. However, data cannot be written to the same
adrress more than once without erasing the block. (Rewrite prohibited)

20.14.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle products (U7, U9)

If the number of Block A or B E/W cycle is already known to exceed 100, set the FMR17 bit in the FMR1
register to "1" (one wait) after reset. When the FMR17 bit is set to "1", one wait state is inserted per
access to Block A or B, regardless of the value of the PM17 bit in the PM1 register. Wait state insertion
during access to all other blocks, as well as to internal RAM, is controlled by PM17, regardless of the
setting of FMR17.
To use the limited number of erasure efficiently, write to unused address within the block instead of
rewrite. Erase block only after all possible address are used. For example, an 8-word program can be
written 128 times before erase becomes necessary.
Maintaining an equal number of erasure between Block A and B will also improve efficiency.
We recommend keeping track of the number of times erasure is used and limiting the number of erasure.

20.14.16 Boot Mode

An indeterminate value is sometimes output in the I/O port until the internal power supply becomes stable
when "H" is applied to the CNV
When setting the CNV
(1) Apply an "L" signal to the RESET pin and the CNV
(2) Bring V
(3) Apply an "H" signal to the CNV
(4) Apply an "H" signal to the RESET pin.
When the CNV
SS

20.14.17 Standard Serial I/O Mode

In flash memory version (128 K + 4 K), a high-level ("H") signal is output from P9
in standard serial I/O mode. In standard serial I/O mode, input an "H" signal to P9
open.
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
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pin and "L" is applied to the RESET pin.
SS
pin to "H", the following procedure is required:
SS
____________
to more than 2.7V, and wait at least 2msec. (Internal power supply stable waiting time)
CC
____________
____________
pin is "H" and RESET pin is "L", P6
page 377
f o 3 8 5
_____________
pin.
SS
pin.
SS
pin is connected to the pull-up resister.
7
20. Precautions
for certain period of time
3
or leave the port
3