Renesas M16C FAMILY series Hardware Manual page 168
16-bit single-chip microcomputer
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Also See for M16C FAMILY series:
- User manual (380 pages) ,
- Hardware manual (257 pages) ,
- Hardware manual (197 pages)
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M
1
6
C
2 /
8
G
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u
p
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M
1
6
C
IT=1 in the G1BCR0 register
(Base timer interrupt generated
by the bit 14 overflow)
IT=0 in the G1BCR0 register
(Base timer interrupt generated
by the bit 15 overflow)
The above applies to the following conditions.
The RST4 bit in the G1BCR0 register is set to "0" (the base timer is not reset by matching the G1BTRR register)
The RST1 bit in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register)
The UD1 to UD0 bits in the G1BCR1 register are set to "00
Figure 13.12 Counter Increment Mode
State of a counter
IT=1 in the G1BCR0 register
(Base timer interrupt generated
by the bit 14 overflow)
b14 overflow signal
Base Timer interrupts
IT=0 in the G1BCR0 register
(Base timer interrupt generated
by the bit 15 overflow)
b15 overflow signal
Base Timer interrupt
Figure 13.13 Counter Increment/Decrement Mode
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0
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2
0
0
7
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0
0
4
7
0 -
2
0
0
2 /
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FFFF
16
C000
16
State of a counter
8000
16
4000
16
0000
16
"1"
b14 overflow signal
"0"
Base Timer interrupts
"1"
b15 overflow signal
"0"
Base Timer interrupt
FFFF
16
C000
16
8000
16
4000
16
0000
16
"1"
"0"
"1"
"0"
page 148
f o
3
8
5
" (counter increment mode)
2
13. Timer S
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