Renesas M16C FAMILY series Hardware Manual page 178

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
(1) Free-running operation
(The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to "0")
Base timer
OUTC1j pin
G1IRj bit
The above applies under the following conditions.
The IVL bit in the G1POCRj register is set to "0" ("L" output as a default value) and the INV bit is set to "0" (not
inversed).
The UD1 to UD0 bits are set to "00
(2) The base timer is reset when the base timer matches either following register
(a) G1PO0
(b) G1BTRR (enabled by setting bit RST4 to "1", and bits RST2 and RST1 to "0")
Base timer
OUTC1j pin
G1IRj bit
The above applies under the following conditions.
The IVL bit in the G1POCRj register is set to "0" ("L" output as a default value) and the INV
bit is set to "0" (not inversed).
The UD1 to UD0 bits are set to "00
Figure 13.22 Single-phase Waveform Output Mode
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
FFFF
16
m
0000
16
m
f
BT1
Inverse
65536
j=0 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
" (counter increment mode).
2
(enabled by setting bit RST1 to "1", and bits RST4 and RST2 to "0"), or
FFFF
16
n+2
m
0000
16
m
n+2-m
f
BT1
Inverse
n+2
f
j = 1 to 7
m: Setting value of the G1POj register
n: Setting value of either G1PO0 register or G1BTRR register
G1IRj bit: Bits in the G1IR register
" (counter increment mode).
2
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f o 3 8 5
65536-m
f
BT1
Inverse
Return to default output level
f
BT1
When setting to "0",
write "0" by program
f
BT1
Inverse
Write "0" by program
BT1
if setting to "0"
Inverse
Return to default
output level
13. Timer S