A/D Converter - Renesas M16C FAMILY series Hardware Manual
16-bit single-chip microcomputer
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Also See for M16C FAMILY series:
- User manual (380 pages) ,
- Hardware manual (257 pages) ,
- Hardware manual (227 pages)
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M
1
6
C
2 /
8
G
o r
u
p
(
M
1
6
C
15. A/D Converter
Note
Ports P0
to P0
4
7
available in M16C/28 (64-pin package). Do not use port P0
to AN2
) and P9
3
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10
AN
), P0
to P0
(AN0
7
0
7
shares the pin with P1
bits are set to "0" (input mode). Note that P1
the 80-pin package.
When not using the A/D converter, set the VCUT bit to "0" (Vref unconnected), so that no current will flow
from the Vref pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the ADi register bits for AN
Table 15.1 shows the A/D converter performance. Figure 15.1 shows the A/D converter block diagram
and Figures 15.2 to 15.4 show the A/D converter associated with registers.
Table 15.1 A/D Converter Performance
Item
A/D Conversion Method
Analog Input Voltage
(2)
Operating Clock f
AD
Resolution
Integral Nonlinearity Error When AV
Operating Modes
Analog Input Pins
Conversion Speed Per Pin
NOTES:
1. Analog input voltage does not depend on use of sample and hold function.
2. Set the φAD frequency to 10 MHz or less. For M16C/28B, set it to 12 MHz or less.
Without sample-and-hold function, set the φAD frequency to 250kH
With the sample and hold function, set the φAD frequency to 1MH
R
e
. v
2
0 .
0
J
a
. n
3
, 1
2
0
0
7
R
E
J
0
9
B
0
0
4
7
0 -
2
0
0
2 /
, 8
M
1
6
C
2 /
8
) B
(AN0
to AN0
), P1
to P1
4
7
0
to P9
(AN2
to AN2
5
7
5
7
to AN0
), and P1
0
7
0
. Therefore, when using these inputs, make sure the corresponding port direction
5
Successive approximation (capacitive coupling amplifier)
(1)
0V to AV
(V
CC
CC
f
/divided-by-2 or f
AD
or f
/divided-by-12 or f
AD
8-bit or 10-bit (selectable)
= Vref = 5V
CC
• With 8-bit resolution: ±2LSB
• With 10-bit resolution: ±3LSB
When AV
= Vref = 3.3V
CC
• With 8-bit resolution: ±2LSB
• With 10-bit resolution: ±5LSB
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat
sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1
8 pins (AN
to AN
0
8 pins (AN
to AN
0
• Without sample and hold function
8-bit resolution: 49 φ
• With sample and hold function
8-bit resolution: 28 φ
page 217
f o
3
8
5
(AN2
to AN2
) and P9
3
0
3
to P0
4
) as analog input pins in M16C/28 (64-pin package.).
to P1
, P9
, P9
to P9
3
3
5
7
to P1
, P9
, P9
to P9
0
3
3
5
i
Performance
)
/divided-by-3 or f
AD
AD
) + 8 pins (AN0
to AN0
) + 8 pins (AN2
7
0
7
) + 4 pins (AN0
to AN0
7
0
cycles, 10-bit resolution: 59 φ
AD
cycles, 10-bit resolution: 33 φ
AD
to P9
(AN2
to AN2
5
7
5
(AN0
to AN0
), P1
7
4
7
0
0
(AN2
to AN2
). Similarly, AD
0
7
(AN2
to AN2
) are available only in
7
0
7
, AN0
, and AN2
pins (i = 0 to 7).
i
i
/divided-by-4 or f
AD
AD
to AN2
) (80pin/85pin package)
0
7
) + 1 pin (AN2
)
(64pin package)
3
4
cycles
AD
cycles
AD
or more.
Z
or more.
Z
15. A/D Converter
) are not
7
to P1
(AN2
3
0
to P10
(AN
to
7
0
____________
input
TRG
/divided-by-6
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