Renesas M16C FAMILY series Hardware Manual page 412

REVISION HISTORY
Rev. Date
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M16C/28 Group (M16C/28, M16C/28B) Hardware Manual
• 16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST)
modified
• 16.6.5 Bits 6, 7: I2C System Clock Select Bits ICK0, ICK1 modified
• Figure 16.20 Address data communication format moved
• (3) Limitation of CPU Clock, 16.14 Precautions modified
Programmable I/O Ports
• Note added
• 17.6 Digital Debounce Function Filter width formula modified
• Figure 17.12 NDDR and P17DDR Register Functions modified, P17DDR reg-
ister: note 1 added
• Figure 17.13 Functioning of Digital Debounce Filter Title added, procedure
note modified
• Table 17.1 Unassigned Pin Handling in Single-chip Mode Note 5 added
• Figure 17.14 Unassigned Pin Handling Note modified
Flash Memory
• 18.1 Flash Memory Performance modified
• Table 18.1 Flash Memory Version Specifications modified, note modified
• 18.2 Memory Map modified
• 18.4 CPU Rewrite Mode modified
• 18.5.1 Flash Memory Control Register 0 (FMR0) FMSTP Bit modified
• 18.5.2 Flash Memory Control Register 1 (FMR1) FMR17 Bit modified
• Figure 18.6 FMR0 and FMR1 Registers FMR0 register: note 3 modified, value
after reset modified; FMR1 register: note 3 modified, reserved bit map modified,
FMR6 modified
• 18.6.3 Interrupts EW1 mode modified
• 18.6.9 Stop Mode modified
• 18.7.5 Block Erase modified
• Figure 18.12 Flow Chart of Block Erase Comman (when not using erase
suspend function) Note 3 modified
• Table 18.7 Pin Functions (Flash Memory Standard Serial I/O Mode) P1
added
• Figure 18.15 Pin Connections for Serial I/O Mode (1) P1
modified
• Figure 18.16 Pin Connections for Serial I/O Mode (2) P1
modified
• Figure 18.17 Circuit Application in Standard Serial I/O Mode 1 P1
added, note 1 modified
• Figure 18.18 Circuit Application in Standard Serial I/O Mode 2 P1
added, note 1 modified
Description
Summary
C-7
pin
6
pin added, note
6
pin added, note
6
pin
6
pin
6