Nmi Interrupt; Key Input Interrupt - Renesas M16C FAMILY series Hardware Manual
16-bit single-chip microcomputer
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M
1
6
C
2 /
8
G
o r
u
p
(
M
1
6
C
______
9.7 NMI Interrupt
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An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the
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NMI interrupt was enabled by writing a "1" to bit 4 of register PM2. The NMI interrupt is a non-maskable
interrupt, once it is enabled.
The input level of this NMI interrupt input pin can be read by accessing the P8 register's P8_5 bit.
_______
NMI is disabled by default after reset (the pin is a GPIO pin, P8
register. Once enabled, it can only be disabled by a reset signal.
_______
The NMI input has an effective digital debounce function for a noise rejection. Refer to "17.6 Digital
Debounce function" for this detail. When using NMI interrupt to exit stop mode, set the NDDR register to
"FF
" before entering stop mode.
16
9.8 Key Input Interrupt
A key input interrupt is generated when input on any of the P10
PD10_7 bits in the PD10 register set to "0" (input) goes low. Key input interrupts can be used as a key-on
wakeup function, the function to exit wait or stop mode. However, if you intend to use the key input interrupt,
do not use P10
to P10
4
interrupt. Note, however, that while input on any pin which has had the PD10_4 to PD10_7 bits set to "0"
(input mode) is pulled low, inputs on all other pins of the port are not detected as interrupts.
Pull-up
transistor
KI
3
Pull-up
transistor
KI
2
Pull-up
transistor
KI
1
Pull-up
transistor
KI
0
Figure 9.12 Key Input Interrupt
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2
0 .
0
J
a
. n
3
, 1
2
0
0
7
R
E
J
0
9
B
0
0
4
7
0 -
2
0
0
2 /
, 8
M
1
6
C
2 /
8
) B
_______
as analog input ports. Figure 9.12 shows the block diagram of the key input
7
PU25 bit in the PUR2
register
PD10_7 bit in the
PD10 register
PD10_7 bit in the PD10 register
PD10_6 bit in the
PD10 register
PD10_5 bit in the
PD10 register
PD10_4 bit in the
PD10 register
page 83
f o
3
8
5
_______
) and can be enabled using bit 4 of PM2
5
_______
to P10
4
7
KUPIC register
Interrupt control circuit
______
pins which has had the PD10_4 to
Key input interrupt
request
9. Interrupts
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