I Flag; Ir Bit; Ilvl2 To Ilvl0 Bits And Ipl - Renesas M16C FAMILY series Hardware Manual

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9.3.1 I Flag

The I flag enables or disables the maskable interrupt. Setting the I flag to "1" (enabled) enables the
maskable interrupt. Setting the I flag to "0" (disabled) disables all maskable interrupts.

9.3.2 IR Bit

The IR bit is set to "1" (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to "0" (interrupt not requested).
The IR bit can be cleared to "0" by program. Note that do not write "1" to this bit.

9.3.3 ILVL2 to ILVL0 Bits and IPL

Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 9.3 shows the settings of interrupt priority levels and Table 9.4 shows the interrupt priority levels
enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag is set to "1"
· IR bit is set to "1"
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. Therefore, they do not affect
one another.
Table 9.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 bits
Level 0 (interrupt disabled)
000
2
Level 1
001
2
010 Level 2
2
011 Level 3
2
100 Level 4
2
101 Level 5
2
110 Level 6
2
111 Level 7
2
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Interrupt priority Priority
level order
Low
High
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Table 9.4 Interrupt Priority Levels Enabled
by IPL
IPL Enabled interrupt priority levels
000
Interrupt levels 1 and above are enabled
2
001
Interrupt levels 2 and above are enabled
2
010
2 Interrupt levels 3 and above are enabled
011
2 Interrupt levels 4 and above are enabled
100
2 Interrupt levels 5 and above are enabled
101
2 Interrupt levels 6 and above are enabled
110
2 Interrupt levels 7 and above are enabled
111
2 All maskable interrupts are disabled
9. Interrupts