Renesas M16C FAMILY series Hardware Manual page 274

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
2
I C0 Control Register 0
b7 b6 b5 b4 b3
NOTES:
1.In the following status, the bit counter is set to "000" automatically
•Start condition/stop condition are detected
•Immediately after the completion of 1-byte data transmit
•Immediately after the completion of 1-byte data receive
Figure 16.4 S1D0 Register
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
b2 b1 b0
Symbol
S1D0
Bit Symbol
Bit counter
BC0
(Number of transmit/receive
bits)
BC1
BC2
2
I C bus interface
ES0
enable bit
ALS Data format select bit
Reserved bit
(b5)
2
I C bus interface
IHR
reset bit
2
I C bus interface pin
TISS
input level select bit
page 254
f o 3 8 5
16. MULTI-MASTER I
Address
02E3
16
Bit Name
b2 b1 b0
0 0
0 0
(1)
0 1
0 1
1 0
1 0
1 1
1 1
0: Disabled
1: Enabled
0: Addressing format
1: Free data format
Set to "0"
0: Reset release (automatic)
1: Reset
2
0: I C bus input
1: SMBUS input
2
C bus INTERFACE
After Reset
00
16
Function RW
0 : 8
RW
1 : 7
0 : 6
1 : 5
0 : 4
RW
1 : 3
0 : 2
1 : 1
RW
RW
RW
RW
RW