Renesas M16C FAMILY series Hardware Manual page 200

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
14.1.1.2 CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i=0 to 2) to select the transfer clock polarity. Figure 14.11
shows the polarity of the transfer clock.
(1) When the CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLK
i
T D
X i
R D
X i
(2) When the CKPOL bit in the UiC0 register is set to "1" (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
CLK
i
T D
X i
R D
X i
NOTES:
1. This applies to the case where the UFORM bit in the UiC0 register is set to "0" (LSB
2. When not transferring, the CLKi pin outputs a high signal.
3. When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
Figure 14.11 Polarity of transfer clock
14.1.1.3 LSB First/MSB First Select Function
Use the UFORM bit in the UiC0 register (i=0 to 2) to select the transfer format. Figure 14.12 shows the
transfer format.
(1) When the UFORM bit in the UiC0 register "0" (LSB first)
CLK
i
T D
X i
R D
X i
(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)
CLK
i
T D
X i
R D
X i
NOTES:
1. This applies to the case where the CKPOL bit in the UiC0 register is
i = 0 to 2
Figure 14.12 Transfer format
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
D0 D D
1 2
D D D
0 1 2
D D D
0 1 2
D D D
0 1 2
first) and the UiLCH bit in the UiC1 register is set to "0" (no reverse).
D0 D
1
D
D 1
0
D
D
7 6
D
D
6
7
set to "0" (transmit data output at the falling edge and the receive
data taken in at the rising edge of the transfer clock) and the UiLCH
bit in the UiC1 register "0" (no reverse).
page 180
f o 3 8 5
D D D D
3 4 5 6
D D D D
3 4 5 6
D D D D
3 4 5 6
D D D D
3 4 5 6
D D D D
2 3 4 5
D D D D
2 3 4 5
D D D D
5 4 3 2
D D D D
5 4 3 2
(2)
D
7
D
7
(3)
D
7
D
7
D D
6 7
D D
6 7
D D
1 0
D D
1 0
14.Serial I/O