Renesas M16C FAMILY series Hardware Manual page 273

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
2
I C 0 D a t a S h i f t R e g i s t e r
b 7 b 6 b 5 b 4
NOTES:
1. Write is enabled only when the ES0 bit in the S1D0 register is "1". Because the same register is used for both
storing transmit/receive data, write the transmit data after the receive data is read out. When the S00 register
is set, the BC2 to BC0 bits in the S1D0 register are set to "000
register are set to "0".
2
I C0 Clock Control Register
b7 b6 b5 b4
Figure 16.3 S00 and S20 Registers
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
b 3 b 2 b 1 b 0
Symbol
S00
Transmit/receive data are stored.
In master transmit mode, the start condition/stop condition are triggered by
writing data to the register (refer to 16.9 START Condition Generation
Method and 16.11 STOP Condition Generation Method). Start transmitting
or receiving data, synchronized with S
b3 b2 b1 b0
Symbol
S20
Bit Symbol
S
CCR0
CCR1
CCR2
CCR3
CCR4
FAST
S
MODE
ACKBIT ACK Bit
ACK-CLK ACK Clock Bit
page 253
f o 3 8 5
Address
02E0
16
Function
.
CL
" and the LRB, AAS and AL bits in the S10
2
Address
02E4
16
Bit Name
Frequency Control Bits
CL
Mode Specification Bit
CL
2
16. MULTI-MASTER I C bus INTERFACE
After Reset
XX
16
After Reset
00
16
Function
See Table 16.3
0: Standard clock mode
1: High-speed clock mode
0: ACK is returned
1: ACK is not returned
0: No ACK clock
1: With ACK clock
RW
RW
(1)
RW
RW
RW
RW
RW
RW
RW
RW
RW