Renesas M16C FAMILY series Hardware Manual page 99

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP
at the time of acceptance of an interrupt request, is even or odd. If the stack pointer
register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time.
Figure 9.8 shows the operation of the saving registers.
NOTES:
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
[SP]
(2) SP contains odd number
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
[SP]
NOTES:
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
Figure 9.8 Operation of Saving Register
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Address Stack
PC
PC
FLG
FLG
H
(Even)
Address Stack
PC
PC
FLG
FLG
H
(Odd)
After registers are saved, the SP content is [SP] minus 4.
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f o 3 8 5
Sequence in which order
registers are saved
L
(2) Saved simultaneously,
all 16 bits
M
L
(1) Saved simultaneously,
PC all 16 bits
H
Finished saving registers
in two operations.
Sequence in which order
registers are saved
(3)
L
M
(4)
L
(1)
PC (2)
H
Finished saving registers
in four operations.
(1)
is even, the FLG
Saved, 8 bits at a time
9. Interrupts
(1)
,