Delayed Trigger Mode 1 - Renesas M16C FAMILY series Hardware Manual

M 1 6 C 2 / 8 G o r u p ( M 1 6 C

15.1.8 Delayed Trigger Mode 1

In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a
digital code. When the input of the AD
conversion is started. After completing the AN
___________
until the second AD
The single sweep conversion of the pins after the AN
trigger mode 1 specifications. Figure 15.24 shows the operation example of delayed trigger mode 1.
Figures 15.25 and 15.26 show each flag operation in the ADSTAT0 register that corresponds to the
operation example. Figure 15.27 shows the ADCON0 to ADCON2 registers in delayed trigger mode 1.
Figure 15.28 shows the ADTRGCON register in delayed trigger mode 1. Table 15.13 shows the trigger
select bit setting in delayed trigger mode 1.
Table 15.12 Delayed Trigger Mode 1 Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation Timing
Analog Input Pin
Readout of A/D Conversion Result
NOTES:
1. Do not generate the next AD
lected pins complete A/D conversion. When an AD
conversion, its trigger is ignored. The falling edge of AD
complete A/D conversion, is considered to be the next AN0 pin conversion start condition.
___________
2. The AD pin falling edge is detected synchronized with the operation clock fAD. Therefore, when the
TRG
___________
AD pin falling edge is generated in shorter periods than fAD, the second AD
TRG
may not be detected. Do not generate the AD
3. Do not write "1" (A/D conversion started) to the ADST bit in delayed trigger mode 1. When write
"1",unexpected interrupts may be generated.
4. AN0 to AN0 and AN2
0 7
need to belong to the same group.
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
___________
TRG
pin falling edge is generated. When the second AD
TRG
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0
bits in the ADCON2 register select pins. Analog voltages applied to the selected
pins are converted one-by-one to a digital code. At this time, the
falling edge starts AN
starts conversion of the pins after AN
AN pin conversion start condition
0
___________
The AD pin input changes state from "H" to "L" (falling edge)
TRG
AN pin conversion start condition
1
___________
The AD pin input changes state from "H" to "L" (falling edge)
TRG
•When the second AD
the AN pin, input voltage of AN
0
falling edge. The conversion of AN
conversion is completed.
___________
•When the AD
TRG
conversion of pins after the AN
•A/D conversion completed
•Set the ADST bit to "0" (A/D conversion halted)
Single sweep conversion completed
Select from AN
and AN to AN
0 7
Readout one of the AN0 to AN7 registers that corresponds to the selected pins
___________
pin falling edge after the AN1 pin conversion is started until all se-
TRG
to AN2 can be used in the same way as AN
0 7
page 242
f o 3 8 5
pin (falling edge) changes state from "H" to "L", a single sweep
pin conversion, the AN
0
pin is restarted. Table 15.12 shows the delayed
1
Specification
pin conversion and the second
0
pin
1
(2)
___________
pin falling edge is generated during A/D conversion of
TRG
pin is sampled or after at the time of AD
1
and the rest of the sweep starts when AN
1
pin falling edge is generated again during single sweep
pin, the conversion is not affected
1
to AN (2 pins), AN to AN
0 1 0
(4)
(8 pins)
___________
pin falling edge is generated again during A/D
TRG
___________
pin, which was input after all selected pins
TRG
___________
pin falling edge in shorter periods than fAD.
TRG
15. A/D Converter
pin is not sampled and converted
1
falling edge is generated,
TRG
___________
AD
pin
TRG
___________
AD
pin falling edge
TRG
(1)
___________
(3)
(4 pins), AN to AN (6 pins)
3 0 5
___________
pin falling edge
TRG
to AN . However, all input pins
0 7
TRG
0