Renesas M16C FAMILY series Hardware Manual page 213

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Table 14.11 Registers to Be Used and Settings in I
Register Bit
U2TB 0 to 7
(1)
U2RB 0 to 7
8
ABT
OER
U2BRG 0 to 7
(1)
U2MR SMD2 to SMD0
CKDIR
IOPOL
U2C0 CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
U2C1 TE
TI
RE
RI
U2IRS
U2RRM,
U2LCH, U2ERE
U2SMR IICM
ABC
BBS
3 to 7
U2SMR2 IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
7
U2SMR3 0, 2, 4 and NODC Set to "0"
CKPH
DL2 to DL0
NOTES:
1. Not all bits in the register are described above. Set those bits to "0" when writing to the registers in I
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Master
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a transfer rate
Set to '010 '
2
Set to "0"
Set to "0"
Select the count source for the U2BRG
register
Invalid because CRD = 1
Transmit buffer empty flag
Set to "1"
Set to "1"
Set to "0"
Set to "1"
Set this bit to "1" to enable transmission
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
Invalid
Set to "0"
Set to "1"
Select the timing at which arbitration-lost Invalid
is detected
Bus busy flag
Set to "0"
Refer to Table 14.13
Set this bit to "1" to enable clock
synchronization
Set this bit to "1" to have SCL
fixed to "L" at the falling edge of the 9th
bit of clock
Set this bit to "1" to have SDA
stopped when arbitration-lost is detected
Set to "0"
Set this bit to "1" to have SCL
forcibly pulled low
Set this bit to "1" to disable SDA
Set to "0"
Refer to Table 14.13
Set the amount of SDA
page 193
f o 3 8 5
2
C bus mode (1) (Continued)
Function
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Invalid
Overrun error flag
Invalid
Set to '010
Set to "1"
Set to "0"
Invalid
Invalid because CRD = 1
Transmit buffer empty flag
Set to "1"
Set to "1"
Set to "0"
Set to "1"
Set this bit to "1" to enable transmission
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
Invalid
Set to "0"
Set to "1"
Bus busy flag
Set to "0"
Refer to Table 14.13
Set to "0"
output Set this bit to "1" to have SCL
2
fixed to "L" at the falling edge of the 9
bit of clock
output Set to "0"
2
Set this bit to "1" to initialize UART2 at
start condition detection
output Set this bit to "1" to have SCL
2
forcibly pulled low
output Set this bit to "1" to disable SDA
2
Set to "0"
Set to "0"
Refer to Table 14.13
digital delay Set the amount of SDA
2
14. Serial I/O
Slave
'
2
output
2
output
2
output
2
digital delay
2
2
C bus mode.
th