Renesas M16C FAMILY series Hardware Manual page 209

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
14.1.2.4 Serial Data Logic Switching Function (UART2)
The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the U2RB register. Figure 14.19 shows serial
data logic.
(1) When the U2LCH bit in the U2C1 register is set to "0" (no reverse)
Transfer clock
TxD
(no reverse)
(2) When the U2LCH bit in the U2C1 register is set "1" (reverse)
Transfer clock
TxD
(reverse)
NOTES:
1. This applies to the case where the CKPOL bit in the U2C0 register
is set to "0" (transmit data output at the falling edge of the transfer
clock), the UFORM bit in the U2C0 register is set to "0" (LSB first),
the STPS bit in the U2MR register is set to "0" (1 stop bit) and the
PRYE bit in the U2MR register is set to "1" (parity enabled).
Figure 14.19 Serial Data Logic Switching
14.1.2.5 TxD and RxD I/O Polarity Inverse Function (UART2)
This function inverses the polarities of the T
input/output data (including the start, stop and parity bits) are inversed. Figure 14.20 shows the T
pin output and R
(1) When the IOPOL bit in the U2MR register is set to "0" (no reverse)
Transfer clock
(no reverse)
(no reverse)
(2) When the IOPOL bit in the U2MR register is set to "1" (reverse)
Transfer clock
(reverse)
(reverse)
NOTES:
1. This applies to the case where the UFORM bit in the U2C0 register
is set to "0"(LSB first), the STPS bit in the U2MR register is set to "0
" (1 stop bit) and the PRYE bit in the U2MR register is set to "1"(
parity enabled).
Figure 14.20 T D and R
X
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
"H"
"L"
"H"
2
ST D0
"L"
"H"
"L"
"H"
2
ST D0
"L"
D pin input polarity inverse.
X
"H"
"L"
TxD "H"
2
ST D0
"L"
RxD "H"
ST D0
2
"L"
"H"
"L"
TxD
"H"
2
ST D0
"L"
"H"
RxD
ST D0
2
"L"
D I/O Polarity Inverse
X
page 189
f o 3 8 5
D1 D2 D3 D4 D5
D1 D2 D3 D4 D5
D2 pin output and R
X
D1 D2 D3 D4 D5
D1 D2 D3 D4 D5
D1 D2 D3 D4 D5
D1 D2 D3 D4 D5
D6 D7 P SP
D6 D7 P SP
ST : Start bit
P : Parity bit
SP : Stop bit
D2 pin input. The logic levels of all
X
D6 D7 P SP
D6 D7 P SP
D6 D7 P SP
D6 D7 P SP
ST : Start bit
P : Parity bit
SP : Stop bit
14. Serial I/O
D
X