Renesas M16C FAMILY series Hardware Manual page 167

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
f
1
Two-phase pulse input
BTS bit in G1BCR1 register
Matched with G1BTRR
Matched with G1PO0 register
Input "L" to INT1 pin
Figure 13.11 Base Timer Block Diagram
Table 13.3 Base Timer Associated Register Settings (Time Measurement Function, Waveform
Generation Function, Communication Function)
Register
G1BCR0 BCK1 to BCK0
RST4
IT
G1BCR1 RST2 to RST1
BTS
UD1 to UD0
G1BT -
G1DV -
Set the following registers to set the RST1 bit to "1" (base timer reset by matching the base timer with the G1PO0 register)
G1POCR0 MOD1 to MOD0
G1PO0 -
G1FS FSC0
G1FE IFE0
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
BCK1 to BCK0
11
or f
2
(n+1) divider
10
RST4
RST1
RST2
Bit
Select a count source
Select base timer reset timing
Select the base timer overflow
Select base timer reset timing
Used to start the base timer
Select how to count
Read or write base timer value
Divide ratio of a count source
Set to "00 " (single-phase waveform output mode)
2
Set reset cycle
Set to "0" (waveform generating function)
Set to "1" (channel operation start)
page 147
f o 3 8 5
f
BT1
Base timer
(Note 1)
Base timer reset
NOTES:
1. Divider is reset when the BTS bit is set to "0".
IT, RST4, BCK1 to BCK0 : Bits in the G1BCR0 register
RST2 to RST1: Bits in the G1BCR1 register
Function
b14 b15
Overflow signal
0 Base timer
overflow request
1
IT
13. Timer S