Table Of Contents - Renesas M16C FAMILY series Hardware Manual
16-bit single-chip microcomputer
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Also See for M16C FAMILY series:
- User manual (380 pages) ,
- Hardware manual (257 pages) ,
- User manual (103 pages)
Table of Contents
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Quick Reference by Address ........................................................................... B-1
1. Overview ......................................................................................................... 1
1.1 Features ........................................................................................................................... 1
1.1.1 Applications ................................................................................................................ 1
1.1.2 Specifications ............................................................................................................. 2
1.2 Block Diagram .................................................................................................................. 4
1.3 Product Information .......................................................................................................... 6
1.4 Pin Assignment ............................................................................................................... 10
1.5 Pin Description ............................................................................................................... 19
2. Central Processing Unit (CPU) ......................................................................22
2.1 Data Registers (R0, R1, R2 and R3) .............................................................................. 22
2.2 Address Registers (A0 and A1) ...................................................................................... 22
2.3 Frame Base Register (FB) .............................................................................................. 23
2.4 Interrupt Table Register (INTB) ....................................................................................... 23
2.5 Program Counter (PC) .................................................................................................... 23
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .......................................... 23
2.7 Static Base Register (SB) ............................................................................................... 23
2.8 Flag Register (FLG) ........................................................................................................ 23
2.8.1 Carry Flag (C Flag) .................................................................................................. 23
2.8.2 Debug Flag (D Flag) ................................................................................................. 23
2.8.3 Zero Flag (Z Flag) ................................................................................................... 23
2.8.4 Sign Flag (S Flag) .................................................................................................... 23
2.8.5 Register Bank Select Flag (B Flag) .......................................................................... 23
2.8.6 Overflow Flag (O Flag) ............................................................................................. 23
2.8.7 Interrupt Enable Flag (I Flag) ................................................................................... 23
2.8.8 Stack Pointer Select Flag (U Flag) ........................................................................... 23
2.8.9 Processor Interrupt Priority Level (IPL) .................................................................... 23
2.8.10 Reserved Area ....................................................................................................... 23
3. Memory ..........................................................................................................24
4. Special Function Register (SFR) ....................................................................25
Table of Contents
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