Address Data Communication; Example Of Master Transmit - Renesas M16C FAMILY series Hardware Manual
16-bit single-chip microcomputer
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16.13 Address Data Communication
This section describes data transmit control when a master transferes data or a slave receives data in 7-bit
address format. Figure 16.20 (1) shows a master transmit format.
Figure 16.20 Address data communication format
16.13.1 Example of Master Transmit
For example, a master transmits data as shown below when following conditions are met: standard clock
mode, SCL clock frequency of 100kHz and ACK clock added.
1) Set s slave address to the 7 high-order bits in the S0D0 register
2) Set "85
" to the S20 register, "000
16
S3D0 registe to generate an ACK clock and set SCL clock frequency t 100 kHz (f
3) Set "00
" to the S10 register to reset transmit/receive
16
4) Set "08
" to the S1D0 register to enable data communication
16
5) Confirm whether the bus is free by BB flag setting in the S10 register
6) Set "E0
" to the S10 register to enter START condition standby mode
16
7) Set the destination address in 7 high-order bits and "0" to a least significant bit in the S00 register
to generate START condition. At this time, the first byte consisting of SCL and ACK clock are
automatically generated
8) Set a transmit data to the S00 register. At this time, SCL and an ACK clock are automatically
generated
9) When transmitting more than 1-byte control data, repeat the above step 8).
10) Set "C0
" in the S10 register to enter STOP condition standby mode if ACK is not returned from
16
the slave receiver or if the transmit is completed
11) Write dummy data to the S00 regiser to generate STOP condition
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(1) A master transmit device transmits data to a receive device
S
R/W
Slave address
"0"
7 bits
(2) A master receive device receives data from a transmit device
S
R/W
Slave address
"1"
7 bits
S :
START condition
A :
ACK bit
2
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Data
Data
A
A
1 - 8 bits
1 - 8 bits
A
A
Data
Data
1 - 8 bits
1 - 8 bits
P
:
STOP condition
R/W :
Read/Write bit
" to the ICK4 to ICK2 bits in the S4D0 register and "00
2
16. MULTI-MASTER I
C bus INTERFACE
A/A
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=8MHz, f
=f1)
IIC
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