Renesas M16C FAMILY series Hardware Manual page 110

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
DMA0 Request Cause Select Register
b7 b6 b5 b4 b3 b2
NOTES:
1. The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0 DMS=0(basic cause of request)
0 0 0 0 Falling edge of INT0 pin
2
0 0 0 1 Software trigger
2
0 0 1 0 Timer A0
2
0 0 1 1 Timer A1
2
0 1 0 0 Timer A2
2
0 1 0 1 Timer A3
2
0 1 1 0 Timer A4
2
0 1 1 1 Timer B0
2
1 0 0 0 Timer B1
2
1 0 0 1 Timer B2
2
1 0 1 0 UART0 transmit
2
1 0 1 1 UART0 receive
2
1 1 0 0 UART2 transmit
2
1 1 0 1 UART2 receive
2
1 1 1 0 A/D conversion
2
1 1 1 1 UART1 transmit
2
Figure 11.2 DM0SL Register
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Symbol
b1 b0
DM0SL
Bit Symbol
DSEL0
DMA request cause
select bit
DSEL1
DSEL2
DSEL3
Nothing is assigned. When write, set to "0".
When read, its content is "0".
(b5-b4)
DMA request cause
DMS
expansion select bit
Software DMA
request bit
DSR
page 90
f o 3 8 5
Address
03B8
16
Bit Name
Refer to note (1)
0: Basic cause of request
1: Extended cause of request
A DMA request is generated by
setting this bit to "1" when the DMS
bit is "0" (basic cause) and the
DSEL3 to DSEL0 bits are "0001
(software trigger).
The value of this bit when read is "0" .
DMS=1(extended cause of request)
IC/OC base timer
–
IC/OC channel 0
IC/OC channel 1
–
–
Two edges of INT0 pin
–
–
–
IC/OC channel 2
IC/OC channel 3
IC/OC channel 4
IC/OC channel 5
IC/OC channel 6
IC/OC channel 7
After Reset
00
16
Function
"
2
11. DMAC
RW
RW
RW
RW
RW
RW
RW