Renesas M16C FAMILY series Hardware Manual page 300

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Figure 16.21 The bit reset timing (The STOP condition detection)
Figure 16.22 The bit reset timing (The START condition detection)
S
CL
PIN bit
Bit reset signal
Bit set signal
Figure 16.23 Bit set/reset timing ( at the completion of data transfer)
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
S
CL
S
DA
BB flag
Bit reset signal
Related bits
MST
TRX
S
CL
S
DA
BB flag
Bit reset signal
Related bits
BC0 - BC2
TRX(slave mode)
page 280
f o 3 8 5
16. MULTI-MASTER I
1.5V
IIC
The bits referring
2V cycle
IIC
The bits referring
1V cycle
IIC
2
C bus INTERFACE
cycle
BC0 - BC2
MST(When in arbitration lost)
to reset
TRX(When in NACK receive in slave
transmit mode)
TRX(ALS=0 meanwhile the slave
to set
receive R/W bit = 1