Renesas M16C FAMILY series Hardware Manual page 156

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Figure 13.1 shows the block diagram of the IC/OC.
BCK1 to BCK0
11
f or f
1 2
Two-phase
10
pulse input
Digital
INPC1
0
filter
Digital
INPC1
1
filter
Digital
INPC1
2
filter
Digital
INPC1
3
filter
Digital
INPC1
4
filter
Digital
INPC1
5
filter
Digital
INPC1
6
filter
Digital
Digital
INPC1
7
filter
debounce
Figure 13.1 IC/OC Block Diagram
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Main clock,
PLL clock,
On-chip
oscillator clock
Request by matching G1BTRR and base timer
Request by matching G1PO0 register and base timer
Request from INT1 pin
BTS
(n+1)
Divider register
(G1DV)
00
10:f
BT1
11: f or f Edge
1 2
select
DF1 to DF0
CTS1 to CTS0
00
10:f
BT1
Edge
11: f or f
1 2
select
DF1 to DF0
CTS1 to CTS0
00
10:f
BT1
11: f or f Edge
1 2
select
DF1 to DF0
CTS1 to CTS0
00
10:f
BT1
11: f or f
1 2 Edge
select
DF1 to DF0
CTS1 to CTS0
00
10:f
BT1
11: f or f Edge
1 2
select
DF1 to DF0
CTS1 to CTS0
00
10:f
BT1
11: f or f
1 2
Edge
select
DF1 to DF0
CTS1 to CTS0
00
0
10:f
BT1
11: f or f
1 2 Edge Gate
1
select function
DF1 to DF0
GT
CTS1 to CTS0
00
0
10:f
BT1
11: f or f
1 2 Edge Gate
1
select function
DF1 to DF0
GT
CTS1 to CTS0
page 136
f o 3 8 5
PCLK0=0
1/2
f or f
1 2
PCLK0=1
Base timer reset
f
BT1
Base timer
Base timer reset
register (G1BTRR)
G1TM0, G1PO0
register
G1TM1, G1PO1
register
G1TM2, G1PO2
register
G1TM3, G1PO3
register
G1TM4, G1PO4
register
G1TM5, G1PO5
register
0
G1TM6, G1PO6
Prescaler
1
function register
PR
0
Prescaler
1
function
PR
BCK1 to BCK0 : Bits in the G1BCR0 register
BTS: Bits in the G1BCR1 register
CTS1 to CTS0, DF1 to DF0, GT, PR : Bits in the G1TMCRj register (j= 0 to 7)
PCLK0 : Bits in the PCLKR register
Base timer over flow request
Base timer interrupt request
Base timer reset request
OUTC1
0
(Note 1)
PWM
output
OUTC1
1
OUTC1
2
PWM
output
OUTC1
3
OUTC1
4
PWM
output
OUTC1
5
OUTC1
6
PWM
output
OUTC1
7
Ch0 to ch7
interrupt request signal
13. Timer S