Renesas M16C FAMILY series Hardware Manual page 54

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
V
CC
ROC
td(P-R)
RESET
CPU clock
Address
Figure 5.2 Reset Sequence
Table 5.1 Pin Status When RESET Pin Level is "L"
Pin name
P0 to P3,
P6 to P10
b15
IPL
Figure 5.3 CPU Register Status After Reset
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
More than
td(ROC)
CPU clock
28 cycles
____________
Status
Input port (high impedance)
b15
0000
0000
0000
0000
0000
0000
0000
b19
00000
16
Content of addresses FFFFE
b15
0000
0000
0000
b15
0000
b8 b7
U I
page 34
f o 3 8 5
FFFFC
Content of reset vector
16
FFFFE
16
b0
16
Data register(R0)
16 Data register(R1)
Data register(R2)
16
16 Data register(R3)
16
Address register(A0)
16 Address register(A1)
16
Frame base register(FB)
b0
Interrupt table register(INTB)
to FFFFC
16 16 Program counter(PC)
b0
User stack pointer(USP)
16
16
Interrupt stack pointer(ISP)
16
Static base register(SB)
b0
16
b0
O B S Z D C
Flag register(FLG)
5. Reset