Renesas M16C FAMILY series Hardware Manual page 67

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
System Clock Control Register 1
b7 b6 b5 b4 b3 b2
0 0 0
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. When entering stop mode from high or middle speed mode, or when the CM05 bit is set to "1" (main clock turned off) in low
speed mode, the CM15 bit is set to "1" (drive capability high).
3. Effective when the CM06 bit is "0" (CM16 and CM17 bits enable).
4. If the CM10 bit is "1" (stop mode), X
pins are placed in the high-impedance state. When the CM11 bit is set to "1" (PLL clock), or the CM20 bit in the CM2 register
is set to "1" (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to "1".
5. After setting the PLC07 bit in the PLC0 register to "1" (PLL operation), wait until tsu (PLL) elapses before setting the CM11 bit to
"1" (PLL clock).
6. When the PM21 bit in the PM2 register is set to "1" (clock modification disable), writing to the CM10, CM11 bits has no effect.
When the PM22 bit in the PM2 register is set to "1" (watchdog timer count source is on-chip oscillator clock), writing to the
CM10 bit has no effect.
7. Effective when CM07 bit is "0" and CM21 bit is "0" .
Figure 7.3 CM1 Register
On-chip Oscillator Control Register
b7 b6 b5 b4 b3
0 0 0
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
Figure 7.4 ROCR Register
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
(1)
b1 b0
Symbol
CM1
Bit Symbol
All clock stop control bit
CM10
(4, 6)
System clock select bit 1
CM11
(6, 7)
Reserved bit
(b4-b2)
X -X
IN OUT
CM15
select bit
(2)
Main clock division
CM16
select bits
CM17
goes "H" and the internal feedback resistor is disconnected. The X
OUT
b2 b1 b0
Symbol
ROCR
Bit Symbol
Frequency Select Bits
ROCR0
ROCR1
Divider Select Bits
ROCR2
ROCR3
(b6-b4) Reserved Bit
Nothing is assigned. When write, set to "0". When read, its
(b7)
content is indeterminate.
page 47
f o 3 8 5
Address After Reset
0007 00100000
16 2
Bit
Name
0 : Clock on
1 : All clocks off (stop mode)
0 : Main clock
1 : PLL clock (Note 5)
"0"
Set to
drive capacity 0 : LOW
1 : HIGH
b7 b6
0 0 : No division mode
(3) 0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
(1)
Address
025C
16
Bit Name
b1 b0
0 0 : f
0 1 : f
1 0 : Do not set to this value
1 1 : f
b3 b2
0 0 : Do not set to this value
0 1 : divide by 2
1 0 : divide by 4
1 1 : divide by 8
Set to "0".
7. Clock Generation Circuit
Function
and X
CIN COUT
After Reset
X0000101
2
Function
(ROC)
1
(ROC)
2
(ROC)
3
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW