Renesas M16C FAMILY series Hardware Manual page 191

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
UARTi Transmit/receive Control Rregister 0 (i=0 to 2)
b7 b6 b5 b4 b3
NOTES:
1. Set the corresponding port direction bit for each CTSi pin to "0" (input mode).
2. Effective when the SMD2 to SMD0 bits in the UMR register to "001
transfer data 8 bits long). Set the UFORM bit to "1" when the SMD2 to SMD0 bits are set to "101
they are set to"100
3. CTS /RTS can be used when the CLKMD1 bit in the UCON register is set to "0" (only CLK
1 1
UCON register is set to "0" (CTS
4. SDA2 and SCL2 are effective when i = 2.
5. When the SMD2 to SMD0 bits in UiMR regiser are set to "000
SCL2 pins are N-channel open-drain output).
6. When the U1MAP bit in PACR register is "1" (P7
7. When the CLK1 and CLK0 bit settings are changed, set the UiBRG register.
UART Transmit/receive Control Register 2
b7 b6 b5 b4
NOTES:
1. To use more than one transfer clock output pins, set the CKDIR bit in the U1MR register to "0" (internal clock).
2. When the U1MAP bit in PACR register is set to "1" (P7
Figure 14.6 U0C0 to U2C0 and UCON Registers
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
b2 b1 b0
Symbol
U0C0 to U2C0
Bit
Bit Name
Symbol
CLK0 BRG count source
(7)
select bit
CLK1
CRS CTS/RTS function
select bit (3)
TXEPT Transmit register empty
flag
CRD CTS/RTS disable bit
Data output select bit
NCH
CKPOL CLK polarity select bit
UFORM Transfer format select bit
(2)
" (UART mode transfer data 7 bits long) or "110
2
/RTS not separated).
0 0
3
b3 b2 b1 b0
Symbol
UCON
Bit Symbol
UART0 transmit interrupt
U0IRS
cause select bit
UART1 transmit interrupt
U1IRS
cause select bit
UART0 continuous
U0RRM
receive mode enable bit
UART1 continuous
U1RRM
receive mode enable bit
UART1 CLK/CLKS
CLKMD0
select bit 0
UART1 CLK/CLKS
CLKMD1
select bit 1
Separate UART0
RCSP
CTS/RTS bit
Nothing is assigned. When write, set to "0".
(b7)
When read, the content is indeterminate
page 171
f o 3 8 5
Address After Reset
03A4 , 03AC , 037C 00001000
16 16 16
b1 b0
0 0 : f or f is selected
1SIO 2SIO
0 1 : f is selected
8SIO
1 0 : f is selected
32SIO
1 1 : Do not set
Effective when CRD is set to "0"
0 : CTS function is selected
1 : RTS function is selected
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
(transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6 , P6 and P7
0 4 3
(5) 0 : TxD2/SDA2 and SCLi pins are CMOS output
1 : TxD2/SDA2 and SCLi pins are N-channel open-drain output
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
0 : LSB first
1 : MSB first
"(clock synchronous serial I/O mode) or "010
2
" ( UART mode transfer data 9 bits long).
2
" (serial I/O disable), do not set NCH bit to "1" (TxDi/SDA2 and
2
to P7 ), CTS/RTS pin in UART1 is assigned to P7
0
Address After Reset
03B0 X0000000
16
Bit Name
0: Transmit buffer empty (Tl = 1)
1: Transmission completed (TXEPT = 1)
0: Transmit buffer empty (Tl = 1)
1: Transmission completed (TXEPT = 1)
0: Continuous receive mode disabled
1: Continuous receive mode enable
0: Continuous receive mode disabled
1: Continuous receive mode enabled
Effective when CLKMD1 bit is set to "1"
0: Clock output from CLK1
1: Clock output from CLKS1
0: Output from CLK1 only
1: Transfer clock output from multiple
(1)
pins function selected
0: CTS/RTS shared pin
1: CTS/RTS separated (CTS
from the P6
to P7 ), CTS is supplied from the P7
3 0 0
2
Function
(1)
(6)
can be used as I/O ports)
" (UART mode
2
2
" (I C bus mode) and "0" when
2
output) and the RCSP bit in the
1
.
0
2
Function RW
RW
RW
RW
RW
RW
RW
supplied RW
0
pin)
4 (2)
pin.
0
14. Serial I/O
RW
RW
RW
RW
RO
RW
RW
(4)
RW
RW