Renesas M16C FAMILY series Hardware Manual page 182

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
(1) Free-running operation
(Bits RST2 and RST1 in the G1BCR0 register and the RST4 bit in the G1BCR1
register are set to 0)
Base timer
OUTC1j pin
G1IRj bit
G1IRk bit
The above applies under the following conditions.
The IVL bit in the G1POCRj register is set to 0 (L output as a default value). The INV bit is set to 0
(not inversed).
Bits UD1 and UD0 are set to 00
(2) Base timer is reset when the base timer matches either following register
(a) G1PO0 (enabled by setting bit RST1 to 1, and bits RST4 and RST2 to 0), or
(b) G1BTRR (enabled by setting bit RST4 to 1, and bits RST2 and RST1 to 0)
Base timer
OUTC1j pin
G1IRj bit
G1IRk bit
The above applies under the following conditions.
The IVL bit in the G1POCRj register is set to 0 (L output as a default value). The INV bit is set to 0 (not
inversed).
Bits UD1 and UD0 are set to 00
Figure 13.24 Set/Reset Waveform Output Mode
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
FFFF
16
n
m
0000
16
n-m
f
BT1
Inverse
j=0, 2, 4, 6 k=j+1
m : Setting value of the G1POj register
G1IRj, G1IRk bits: Bits in the G1IR register
(counter increment mode).
2
FFFF
16
p+2
n
m
0000
16
n-m
f
BT1
Write 0 by program
if setting to 0
j=2, 4, 6 k=j+1
m : Setting value of the G1POj register
p: Setting value of either register G1PO0 or G1BTRR
G1IRj, G1IRk bits: Bits in the G1IR register
(counter increment mode).
2
page 162
f o 3 8 5
65536-n+m
f
BT1
Inverse
65536
f
BT1
Write 0 by program
if setting to 0
inverse
n: Setting value of the G1POk register
p+2-n+m
f
BT1
When setting to 0,
write 0 by program
n: Setting value of the G1POk register
13. Timer S
Return to default
output level
Return to default output level