Renesas M16C FAMILY series Hardware Manual page 242

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Timer B2 Special Mode Register
b7 b6 b5 b4 b3 b2
0 0
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this
bit to "0" (Timer B2 underflow).
3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), set the PD8_5
bit to "0" (= input mode).
4. Associated pins are U(P8
to the SD pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-
impedance state. If a low-level ("L") signal is applied to the SD pin, three-phase motor control timer output will
be disabled (INV03=0). At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become
programmable I/O ports. When the IVPCR1 bit is set to 1, pins U, U, V, V, W, and W are placed in a high-
impedance state regardless of which function of those pins is used.
5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1" (A/D trigger mode).
6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]),
set the INV02 bit to "1" (three-phase motor control timer function).
7. Refer to "17.6 Digital Debounce Function" for the SD input
Figure 15.5 TB2SC Register
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
(1)
b1 b0
Symbol Address
TB2SC 039E
Bit Symbol
Timer B2 reload timing
PWCOM
switch bit
Three-phase output port
IVPCR1
SD control bit 1
Timer B0 operation mode
TB0EN
select bit
Timer B1 operation mode
TB1EN
select bit
TB2SEL Trigger select bit
Reserved bit
(b6-b5)
Nothing is assigned. When write, set to "0".
(b7)
When read, its content is "0"
), U(P8 ), V(P7
0 1 2
page 222
f o 3 8 5
After Reset
X0000000
16
Bit Name
0 : Timer B2 underflow
(2)
1 : Timer A output at odd-numbered
0 : Three-phase output forcible cutoff
by SD pin input (high impedance)
disabled
(3, 4, 7)
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
0 : Other than A/D trigger mode
1 : A/D trigger mode
0 : Other than A/D trigger mode
1 : A/D trigger mode
0 : TB2 interrupt
(6)
1 : Underflow of TB2 interrupt generation
frequency setting counter [ICTB2]
Set to "0"
), V(P7 ), W(P7 ), W(P7 ). When a high-level ("H") signal is applied
3 4 5
15. A/D Converter
2
Function
(5)
(5)
RW
RW
RW
RW
RW
RW
RW