Renesas M16C FAMILY series Hardware Manual page 81

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Main clock oscillation
PLL operation mode
CPU clock: f(PLL)
CM07=0
CM06=0
CM17=0
CM16=0
CM04=1 CM04=0
PLL operation
mode
CPU clock: f(PLL)
CM07=0
CM06=0
CM17=0
CM16=0
Sub clock oscillation
: Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown.
NOTES:
1. Avoid making a transition when the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Wait for the main clock oscillation stabilization time before switching over.
3. Switch clock after oscillation of sub-clock is sufficiently stable.
4. Change bits CM17 and CM16 before changing the CM06 bit.
5. The PM20 bit in the PM2 register becomes effective when the PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20 bit when the PLC07 bit is set to 0 (PLL off).
Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz.
6. Set the CM06 bit to 1 (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.
7. When the CM21 bit is set to 0 (on-chip oscillator turned off) and the CM05 bit is set to 1 (main clock turned off), the CM06 bit is fixed to 1 (divide-by-8 mode) and the
CM15 bit is fixed to 1 (drive capability High).
Figure 7.12 State Transition in Normal Mode
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Middle-speed mode
PLC07=1
High-speed mode (divide by 2)
CM11=1
(5) CPU clock: f(X )
IN CPU clock: f(X )/2
IN
CM07=0 CM07=0
CM06=0 CM06=0
CM17=0 CM17=0
PLC07=0
CM11=0
CM16=0 CM16=1
(5)
CM04=1
Middle-speed mode
PLC07=1 High-speed mode
(divide by 2)
CM11=1
(5)
CPU clock: f(X ) CPU clock: f(X )/2
IN IN
CM07=0 CM07=0
CM06=0 CM06=0
PLC07=0
CM17=0 CM17=0
CM11=0
CM16=0 CM16=1
(5)
CM07=1
(3)
CM05=1
(1, 7)
Low power dissipation mode
page 61
f o 3 8 5
Middle-speed mode Middle-speed mode Middle-speed mode
(divide by 4) (divide by 8) (divide by 16)
CPU clock: f(X )/4
IN
CPU clock: f(X )/8 CPU clock: f(X
IN IN
CM07=0 CM07=0
CM07=0
CM06=0 CM06=0
CM17=1 CM17=1
CM06=1
CM16=0 CM16=1
CM04=0
Middle-speed mode
Middle-speed mode Middle-speed mode
(divide by 4)
(divide by 8) (divide by 16)
CPU clock: f(X )/4 CPU clock: f(X )/8 CPU clock: f(X )/16
IN IN IN
CM07=0 CM07=0
CM07=0
CM06=0 CM06=0
CM17=1 CM17=1
CM06=1
CM16=0 CM16=1
CM07=0
(2, 4)
Low-speed mode
CM21=0
CPU clock: f(X )
CIN
CM07=0
CM21=1
CM05=0
CPU clock: f(X )
CIN
CM07=0
CM06=1
CM15=1
7. Clock Generation Circuit
On-chip oscillator clock
oscillation
On-chip oscillator mode
CPU clock
CM21=0
CM05=0
)/16
(2, 6)
f(ROC)
f(ROC)/2
f(ROC)/4
f(ROC)/8
CM05=1
f(ROC)/16
CM21=1
(1)
CM04=1 CM04=0
On-chip oscillator
mode
CM21=0 CPU clock
CM05=0 M M0
(6)
f(ROC)
f(ROC)/2
f(ROC)/4
f(ROC)/8
f(ROC)/16
CM21=1
CM05=1
(1)
CM07=1 CM07=0
(3) (4)
Low-speed
mode
CPU clock: f(X )
CIN
CM07=0
On-chip oscillator low power
dissipation mode
CPU clock
f(ROC)
f(ROC)/2
f(ROC)/4
f(ROC)/8
f(ROC)/16
CM04=1 CM04=0
On-chip oscillator
low power
dissipation mode
CPU clock
f(ROC)
f(ROC)/2
f(ROC)/4
f(ROC)/8
f(ROC)/16