Interrupt Response Time; Variation Of Ipl When Interrupt Request Is Accepted - Renesas M16C FAMILY series Hardware Manual
16-bit single-chip microcomputer
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9.4.1 Interrupt Response Time
Figure 9.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes the time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of the time from when an interrupt request is generated till
when the instruction then executing is completed ((a) in Figure 9.6) and the time during which the inter-
rupt sequence is executed ((b) in Figure 9.6).
Interrupt request generated
(a) The time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) The time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Figure 9.6 Interrupt response time
9.4.2 Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 9.5 is set in the IPL. Shown in Table 9.5 are the IPL values of software and special interrupts
when they are accepted.
Table 9.5 IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Interrupt sources
Watchdog timer, NMI, Oscillation stop and re-oscillation detection,
low voltage detection
Software, address match, DBC, single-step
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Interrupt request acknowledged
Instruction
Interrupt sequence
(a)
Interrupt response time
Interrupt vector address
Even
Even
Odd
Odd
_______
_________
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(b)
SP value
Without wait
Even
18 cycles
Odd
19 cycles
Even
19 cycles
Odd
20 cycles
Time
Instruction in
interrupt routine
Level that is set to IPL
7
Not changed
9. Interrupts
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