Renesas M16C FAMILY series Hardware Manual page 381

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20.6.1.3 Timer A (One-shot Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR
register before setting the TAiS bit in the TABSR register to "1" (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register are modified while the TAiS bit remains "0" (count stops) regardless whether after
reset or not.
2. When setting TAiS bit to "0" (count stop), the followings occur:
• A counter stops counting and a content of reload register is reloaded.
• TAi pin outputs "L".
OUT
• After one cycle of the CPU clock, the IR bit in TAiIC register is set to "1" (interrupt request).
3. Output in one-shot timer mode synchronizes with a count source internally generated. When the
external trigger has been selected, a maximun delay of one cycle of the count source occurs be-
tween the trigger input to TAi
4. The IR bit is set to "1" when timer operation mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
• Change an operation mode from timer mode to one-shot timer mode.
• Change an operation mode from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (the IR bit), set the IR bit to "0" after the changes listed above have
been made.
5. When a trigger occurs while the timer is counting, the counter reloads the reload register value, and
continues counting after a second trigger is generated and the counter is decremented once. To
generate a trigger while counting, space more than one cycle of the timer count source from the first
trigger and generate again.
6. When selecting the external trigger for the count start conditions in timer A one-shot timer mode, do
not generate an external trigger 300ns before the count value of timer A is set to "0000
shot timer may stop counting.
7. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to "1"
(three-phase output forcible cutoff by input on SD pin enabled), the TA1
pins go to a high-impedance state.
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
pin and output in one-shot timer mode.
IN
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20. Precautions
". The one-
16
, TA2 and TA4
OUT OUT OUT