Renesas M16C FAMILY series Hardware Manual page 158

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Divider Register
b7 b6 b5 b4 b3
Base Timer Control Register 1
b7 b6 b5 b4 b3
0 0
NOTES:
1. The base timer is reset two f
G1PO0 register. (See Figure 13.7 for details on the G1PO0 register) When the RST1 bit is set to
"1", the value of the G1POj register (j=1 to 7) for the waveform generating function must be set to a
value smaller than that of the G1PO0 register.
When the RST1 bit is set to "1", set the RST4 bit in the G1BCR0 register to "0".
Figure 13.3 G1DV Register and G1BCR1 Register
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
b2 b1 b0
Symbol
G1DV
Divide f , f or two-phase pulse input by (n+1)
1 2
for f clock cycles generation.
BT1
n: the setting value of the G1DV register
b2 b1 b0
Symbol
G1BCR1
0
Bit
Symbol
Reserved Bit
(b0)
Base Timer Reset
RST1
Cause Select Bit 1
Base Timer Reset
RST2
Cause Select Bit 2
Reserved Bit
(b3)
BTS Base Timer Start Bit
UD0
Counter Increment/
Decrement Control Bit
UD1
Reserved Bit
(b7)
clock cycles after the base timer matches the value set in the
BT1
page 138
f o 3 8 5
Address
032A
16
Function
Address
0323
16
Bit Name
Set to "0".
0: The base timer is not reset by
matching the G1PO0 register
1: The base timer is reset by matching
with the G1PO0 register
0: The base timer is not reset by
applying "L" to the INT1 pin
1: The base timer is reset by applying "L"
to the INT1 pin
Set to "0".
0: Base timer is reset
1: Base timer starts counting
b6 b5
0 0 : Counter increment mode
0 1 : Counter increment/decrement mode
1 0 : Two-phase pulse signal processing
mode
1 1 : Do not set to this value
Set to "0".
13. Timer S
After Reset
00
16
Setting range RW
00 to FF RW
16 16
After Reset
00
16
Function RW
RW
RW
(1)
RW
RW
RW
RW
RW
RW