Renesas M16C FAMILY series Hardware Manual page 180
16-bit single-chip microcomputer
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Also See for M16C FAMILY series:
- User manual (380 pages) ,
- Hardware manual (257 pages) ,
- Hardware manual (468 pages)
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M
1
6
C
2 /
8
G
o r
u
p
(
M
1
6
C
(1) Free-running operation
(The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to "0")
Base timer
OUTC1j pin
G1IRj bit
The above applies under the following conditions.
The IVL bit in the G1POCRj register is set to "0" ("L" output as a default value). The INV bit
is set to "0" (not inversed).
The UD1 to UD0 bits are set to "00
(2) Base timer is reset when the base timer matches either following register
(a) G1PO0 (enabled by setting bit RST1 to "1", and bits RST4 and RST2 to "0"), or
(b) G1BTRR (enabled by setting bit RST4 to "1", and bits RST2 and RST1 to "0")
Base timer
OUTC1j pin
G1IRj bit
The above applies under the following conditions.
The IVL bit in the G1POCRj register is set to "0" ("L" output as a default value).
The INV bit is set to "0" (not inversed).
The UD1 to UD0 bits are set to "00
Figure 13.23 Phase-delayed Waveform Output Mode
R
e
. v
2
0 .
0
J
a
. n
3
, 1
2
0
0
7
R
E
J
0
9
B
0
0
4
7
0 -
2
0
0
2 /
, 8
M
1
6
C
2 /
8
) B
FFFF
16
m
0000
16
j=0 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
" (counter increment mode).
2
FFFF
16
n+2
m
0000
16
m
f
BT1
j=1 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
" (counter increment mode).
2
page 160
f o
3
8
5
65536
f
BT1
Inverse
65536X2
Write "0" by program
if setting to "0"
n+2
n+2
f
f
BT1
BT1
Inverse
Inverse
Write "0" by program
if setting to "0"
n: Setting value of either register G1PO0 or G1BTRR
65536
f
BT1
Inverse
f
BT1
Inverse
13. Timer S
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