Renesas M16C FAMILY series Hardware Manual page 217

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
14.1.3.1 Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDA
to low while the SCL
when the SDA
Because the start and stop condition-detected interrupts share the interrupt control register and vec-
tor, check the U2SMR register's BBS bit to determine which interrupt source is requesting the inter-
rupt.
3 to 6 cycles < setup time
3 to 6 cycles < hold time
(
Start condition)
(
Stop condition)
NOTES:
1. When the PCLK1 bit in the PCLKR register is set to "1", the cycles indicates
the f1SIO's generation frequency cycles; when PCLK1 bit is set to "0", the
cycles indicated the f2SIO's generation frequency cycles.
Figure 14.24 Detection of Start and Stop Condition
14.1.3.2 Output of Start and Stop Condition
A start condition is generated by setting the STAREQ bit in the U2SMR4 register to "1" (start).
A restart condition is generated by setting the RSTAREQ bit in the U2SMR4 register to "1" (start).
A stop condition is generated by setting the STPREQ bit in the U2SMR4 register to "1" (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to "1" (start).
(2) Set the STSPSEL bit in the U2SMR4 register to "1" (output).
Make sure that no interrupts or DMA transfers will occur between (1) and (2).
The function of the STSPSEL bit is shown in Table 14.14 and Figure 14.25.
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
pin is in the high state. A stop condition-detected interrupt request is generated
2
pin changes state from low to high while the SCL
2
(1)
(1)
SCL2
SDA2
SDA2
page 197
f o 3 8 5
Hold time
Setup time
pin changes state from high
2
pin is in the high state.
2
14. Serial I/O