Renesas M16C FAMILY series Hardware Manual page 261

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
A/D Trigger Control Register
b7 b6 b5 b4
NOTES:
1. If ADTRGCON reigster is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 15.23 ADTRGCON Register in Delayed Trigger Mode 0
Table 15.11 Trigger Select Bit Setting in Delayed Trigger Mode 0
TRG TRG1
0
0
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
(1)
b3 b2 b1 b0
Symbol
1 1 1 1
ADTRGCON
Bit Symbol
A/D Operation Mode
SSE
Select Bit 2
A/D Operation Mode
DTE
Select Bit 3
AN0 Trigger Select Bit
HPTRG0
AN1 Trigger Select Bit
HPTRG1
Nothing is assigned. When write, set to "0".
(b7-b4)
When read, its content is "0".
HPTRG1
HPTRG0
1
1
page 241
f o 3 8 5
Address After Reset
03D2 00
16 16
Bit Name
Simultaneous sample sweep mode or
delayed trigger mode 0,1
Delayed trigger mode 0, 1
Refer to Table 15.11
Refer to Table 15.11
Trigger
Timer B0, B1 underflow
15. A/D Converter
Function RW
RW
RW
RW
RW