REVISION HISTORY
Rev.
Date
Page
15
22
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26
27
28
30
30
35
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39
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58
60
M16C/28 Group (M16C/28, M16C/28B) Hardware Manual
TB0 to TB2, TB0MR to TB2MR, U0BRG, U0TB, U0RB, U1BRG, U1TB, U1RB,
AD0 to AD7, ADTRGCON, ADSTAT0, ADCON0, P0 to P3, and P6 to P10 regis-
ters revised
• Table 4.1 SFR Infromation (1) Note 3 modified
Reset
• 5.1.2 Hardware Reset 2 modified
• Figure 5.4 Voltage Detection Circuit Block modified
• 5.5 Voltage Detection Circuit Note added, information partially deleted
• (Figure 5.5.2 WDC Register) Figure deleted
• Figure 5.5 VCR1 Register, VCR2 Register, and D4INT Register Voltage
detection register 2: former note 4 deleted, b5-b4 revised; Voltage down detec-
tion interrupt register: (4) of note 5 added
• Figure 5.6 Typical Operation of Hardware Reset 2 revised
• 5.5.1 Voltage Detection Interrupt modified
• 5.5.2 Limitations on Stop Mode modified
• 5.5.3 Limitations on WAIT Instruction modified
Processor Mode
• Figure 6.2 PM1 Register Reserved bit map modified, note 2 modified
Clock Generation Circuit
• Figure 7.3 CM1 Register Note 6 modified
• Figure 7.4 ROCR Register b7-b4 revised
• Figure 7.6 PCLKR Register and PM2 Register PCLKR Register: PCLK0 and
PCLK1 modified; PM2 Register: reserved bit map modified, note 2 and note 4
modified
• 7.1 Main Clock modified
• 7.3 On-chip Oscillator Clock modified
• 7.5.2 Peripheral Function Clock(f
• Table 7.3 Setting Clock Related Bit and Modes modified
• Table 7.4 Interrupts to Exit Wait Mode Timer S added
• 7.6.3.1 Entering Stop Mode modified
• Figure 7.11 State Transition to Stop Mode and Wait Mode Figure revised,
description added, note 5 modified
• Figure 7.12 State Transition in Normal Mode description added
• Table 7.5 Allowed Transition and Setting note 1 and note 2 modified
Protection
• NDDR register added
Interrupt
• Table 9.1 Fixed Vector Tables note 2 added
• 9.3 Interrupt Control IFSR21 bit added
Description
Summary
, f
, f
, f
1
2
8
C-2
, f
, f
, f
, fc
32
2SIO
8SIO
AD
) modified
32