Renesas M16C FAMILY series Hardware Manual page 208

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
14.1.2.2 Counter Measure for Communication Error
If a communication error occurs while transmitting or receiving in UART mode, follow the procedure
below.
• Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to "0" (reception disabled)
(2) Set the RE bit in the UiC1 register to "1" (reception enabled)
• Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in UiMR register "000
(2) Set the SMD2 to SMD0 bits in UiMR register "001
(3) "1" is written to TE bit in the UiC1 register (reception enabled), regardless of the TE bit
14.1.2.3 LSB First/MSB First Select Function
As shown in Figure 14.18, use the UFORM bit in the UiC0 register to select the transfer format. This
function is valid when transfer data is 8 bits long.
(1) When the UFORM bit in the UiC0 register is set to "0" (LSB first)
CLK
i
T D
X i
R D
X i
(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)
CLK
i
T D
X i
R D
X i
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
NOTES:
1. This applies to the case where the CKPOL bit in the UiC0 register is set to "0" (transmit data output at the
falling edge and the receive data taken in at the rising edge of the transfer clock), the UiLCH bit in the UiC1
register is set to "0" (no reverse), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the PRYE bit
in the UiMR register is set to "1" (parity enabled).
Figure 14.18 Transfer Format
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
ST D0 D
1
ST
D D
0 1
D
ST D
7 6
D
ST D
7 6
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f o 3 8 5
" (Serial I/O disabled)
2
", "101
2
D D D D
2 3 4 5
D D D D
2 3 4 5
D D D D
5 4 3 2
D D D D
5 4 3 2
", "110 "
2 2
D D P SP
6 7
D D P SP
6 7
D D
P SP
1 0
D D
1 0 P SP
14.Serial I/O