Renesas M16C FAMILY series Hardware Manual page 215

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
2
Table 14.13 I C bus Mode Functions
Function
Factor of interrupt number
(1)
10 (Refer to Fig.14.23)
Factor of interrupt number
(1)
15 (Refer to Fig.14.23)
Factor of interrupt number
(1)
16 (Refer to Fig.14.23)
Timing for transferring data
from the UART reception
shift register to the U2RB
register
UART2 transmission
output delay
Functions of P7 pin
0
Functions of P7 pin
1
Functions of P7 pin
2
Noise filter width
Read RxD2 and SCL pin
2
levels
Initial value of TxD2 and
SDA outputs
2
Initial and end values of
SCL
2
DMA1 factor (Refer to Fig.
14.23)
Store received data
Read received data
NOTES:
1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt
may inadvertently be set to "1" (interrupt requested). (Refer to "Notes on interrupts" in Precautions.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore,
always be sure to clear the IR bit to "0" (interrupt not requested) after changing those bits
SMD2–the SMD0 bits in the U2MR register, the IICM bit in the U2SMR register,
the IICM2 bit in the U2SMR2 register, the CKPH bit in the U2SMR3 register
2. Set the initial value of SDA
disabled).
3. Second data transfer to U2RB register (Rising edge of SCL
4. First data transfer to U2RB register (Falling edge of SCL
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Clock synchronous serial I/O
mode (SMD2 to SMD0 = 001
IICM = 0)
UART2 transmission
Transmission started or
completed (selected by U2IRS)
UART2 reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Not delayed
TxD2 output
RxD2 input
CLK2 input or output selected
15 ns
Possible when the
corresponding port direction bit
= 0
CKPOL = 0 (H)
CKPOL = 1 (L)
UART2 reception
1st to 8th bits are stored in
the bit 7 to bit 0 in the U2RB
register
U2RB register status is read
directly as is
output while the SMD2 to SMD0 bits in the U2MR register is set to "000
2
page 195
f o 3 8 5
2
I C bus mode (SMD2 to SMD0 = 010
,
2
IICM2 = 0
(NACK/ACK interrupt)
CKPH = 0 CKPH = 1
(No clock delay) (Clock delay)
Start condition detection or stop condition detection
(Refer to Table 14.14)
No acknowledgment
detection (NACK)
Rising edge of SCL 9th bit
2
Acknowledgment detection
(ACK)
Rising edge of SCL 9th bit
2
Rising edge of SCL 9th bit
2
Delayed
SDA input/output
2
SCL input/output
2
(Cannot be used in I
200 n s
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I
H L
Acknowledgment detection
(ACK)
1st to 8th bits are stored in
the bit 7 to bit 0 in the U2RB
register
.
9th bit)
2
9th bit)
2
, IICM = 1)
2
IICM2 = 1
(UART transmit/ receive interrupt)
CKPH = 0 CKPH = 1
(Clock delay)
(No clock delay)
UART2 transmission UART2 transmission
Rising edge of Falling edge of SCL
SCL 9th bit next to the 9th bit
2
UART2 transmission
Falling edge of SCL 9th bit
2
Falling and rising
Falling edge of
edges of SCL
SCL 9th bit
2
bit
2
C bus mode)
2
C bus mode
H L
UART2 reception
Falling edge of SCL 9th bi
t
2
1st to 7th bits are stored into the bit 6 to
bit 0 in the U2RB register, with 8th bit
stored in the bit 8 in the U2RB register
1st to 8th bits are
stored in U2RB
register bit 7 to bit 0
(3)
Read U2RB register
Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
(4)
bit 0
.
" (serial I/O
2
14. Serial I/O
2
9th
2
(2)