Renesas M16C FAMILY series Hardware Manual page 234

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Table 14.20 SI/O3 and SI/O4 Specifications
Item
Transfer data format
Transfer clock
Transmission/reception
start condition
Interrupt request
generation timing
CLKi pin fucntion
S i pin function
OUT
SINi pin function
Select function
NOTES:
1. To set the SMi6 bit in the SiC register to "0" (external clock), follow the procedure described below.
• If the SMi4 bit in the SiC register is set to "0", write transmit data to the SiTRR register while input on the CLKi
pin is high. The same applies when rewriting the SMi7 bit in the SiC register.
• If the SMi4 bit is set to "1", write transmit data to the SiTRR register while input on the CLKi pin is low. The
same applies when rewriting the SMi7 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the
transfer clock after supplying eight pulses. If the SMi6 bit is set to "1" (internal clock), the transfer clock
automatically stops.
2. Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. Therefore,
do not write the next transmit data to the SiTRR register during transmission.
3. When the SMi6 bit in the SiC register is set to "1" (internal clock), S
clock period after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit
data is written to the SiTRR register during this period, S
the data hold time thereby reduced.
4. When the SMi6 bit in the SiC register is set to "1" (internal clock), the transfer clock stops in the high state if the
SMi4 bit is set to "0", or stops in the low state if the SMi4 bit is set to "1".
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
• Transfer data length: 8 bits
• The SMi6 bit in the SiC (i=3, 4) register is set to "1" (internal clock) : fj/ (2(n+1))
fj = f , f , f
1SIO 2SIO
• SMi6 bit is set to "0" (external clock) : Input from CLKi pin
• Before transmission/reception can start, the following requirements must be met
Write transmit data to the SiTRR register
• When the SMi4 bit in the SiC register is set to "0"
The rising edge of the last transfer clock pulse
• When SMi4 is set to "1"
The falling edge of the last transfer clock pulse
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
I/O port, receive data input
• LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Function for setting an S
When the SMi6 bit in the SiC register is set to "0" (external clock), the S
output level while not tranmitting can be selected.
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge of
transfer clock can be selected.
page 214
f o 3 8 5
Specification
, f . n=Setting value of SiBRG register
8SIO 32SIO
(2, 3)
i initial value set function
OUT
OUTi
immediately goes to a high-impedance state, with
OUTi
00
16
(1)
(4)
(4)
retains the last data for a 1/2 transfer
14. Serial I/O
to FF .
16
i pin
OUT