Renesas M16C FAMILY series Hardware Manual page 226

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
(1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select)
Transfer clock
TxD2
RxD2
Timer A0
(2) The ACSE bit in the U2SMR register (auto clear of transmit enable bit)
Transfer clock
TxD2
RxD2
BCNIC register
IR bit (Note)
U2C1 register
TE bit
(3) The SSS bit in the U2SMR register (Transmit start condition select)
If SSS bit is set to "0", the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
TxD2
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxD2
CLK2
TxD2
RxD2
NOTES:
1: The falling edge of RxD2 when the IOPOL is set to "0"; the rising edge of RxD2 when the IOPOL is set to "1".
2: The transmit condition must be met before the falling edge (Note 1) of RxD.
This diagram applies to the case where the IOPOL is set to "1" (reversed)
Figure 14.30 Bus Collision Detect Function-Related Bits
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
ST D0
Input to TA0
ST D0
ST D0
ST D0
(Note 2)
page 206
f o 3 8 5
D1 D2 D3 D4
IN
If ABSCS is set to "1", bus collision is determined when timer
A0 (one-shot timer mode) underflows
D1 D2 D3 D4
D1 D2 D3 D4
D1 D2 D3 D4
.
D5 D6 D7 D8
.
D5 D6 D7 D8
If ACSE bit is set to "1"
automatically clear when bus collision
occurs), the TE bit is cleared to "0"
(transmission disabled) when
the IR bit in the BCNIC register is
set to "1" (unmatching detected).
D5 D6 D7 D8
D5 D6 D7 D8
14. Serial I/O
SP
SP
SP
SP