Renesas M16C FAMILY series Hardware Manual page 121

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Timer Ai Register (i= 0 to 4)
(b15)
b7
NOTES:
1. The register must be accessed in 16 bit units.
2. If the TAi register is set to '0000
requests are not generated either. Furthermore, if "pulse output" is selected, no pulses are
output from the TAiOUT pin.
3. If the TAi register is set to '0000
level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated
either. The same applies when the 8 high-order bits of the timer TAi register are set to '000
0
16
4. Use the MOV instruction to write to the TAi register.
5. The timer counts pulses from an external device or overflows or underflows in other timers.
Count Start Flag
b7 b6 b5
Up/down Flag
b7 b6 b5
NOTES:
1. Use MOV instruction to write to this register.
2: Make sure the port direction bits for the TA2
"0" (input mode).
3. When not using the two-phase pulse signal processing function, set the corresponding bit to "0".
Figure 12.5 TA0 to TA4 Registers, TABSR Register, and UDF Register
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
(1)
(b8)
b0 b7 b0
Mode
Timer Divide the count source by n + 1 where n =
mode set value
Event
Divide the count source by FFFF
counter
where n = set value when counting up or
mode
by n + 1 when counting down
One-shot Divide the count source by n where n = set
timer mode value and cause the timer to stop
Modify the pulse width as follows:
Pulse width
PWM period: (2
modulation
High level PWM pulse width: n / fj
mode
where n = set value, fj = count source
(16-bit PWM)
frequency
Pulse width
Modify the pulse width as follows:
modulation PWM period: (2
mode High level PWM pulse width: (m + 1)n / fj
(8-bit PWM)
where n = high-order address set value,
m = low-order address set value, fj =
count source frequency
,' the counter does not work and timer Ai interrupt
16
,' the pulse width modulator does not work, the output
16
' while operating as an 8-bit pulse width modulator.
Symbol
b4 b3 b2 b1 b0
TABSR
Bit Symbol
TA0S Timer A0 count start flag
TA1S Timer A1 count start flag
TA2S Timer A2 count start flag
TA3S Timer A3 count start flag
TA4S Timer A4 count start flag
TB0S Timer B0 count start flag
TB1S Timer B1 count start flag
TB2S Timer B2 count start flag
(1)
Symbol
b4 b3 b2 b1 b0
UDF
Bit Symbol
Timer A0 up/down flag
TA0UD
TA1UD
Timer A1 up/down flag
TA2UD
Timer A2 up/down flag
TA3UD
Timer A3 up/down flag
Timer A4 up/down flag
TA4UD
Timer A2 two-phase pulse
TA2P
signal processing select bit
TA3P
Timer A3 two-phase pulse
signal processing select bit
Timer A4 two-phase pulse
TA4P
signal processing select bit
page 101
f o 3 8 5
Symbol Address
TA0 0387 , 0386
16 16
TA1 0389 , 0388
16 16
TA2 038B , 038A
16 16
TA3 038D , 038C
16 16
TA4 038F , 038E
16 16
Function
– n + 1
16
(5)
16 – 1) / fj
8
– 1) x (m + 1)/ fj
Address After Reset
0380 00
16 16
Bit Name Function
0 : Stops counting
1 : Starts counting
Address After Reset
0384 00
16 16
Bit Name Function
0 : Down count
1 : Up count
Enabled by setting the MR2 bit in
the TAiMR register to "0"
(= switching source in UDF
register) during event counter
mode.
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
to TA4I and TA2 to TA4
IN N OUT
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
RW
Setting Range
0000 to FFFF RW
16 16
0000 to FFFF
16 16
RW
0000 to FFFF
16 16
WO
(2, 4)
0000 to FFFE
16 16
(3, 4)
WO
00 to FE
16 16
(High-order address)
00 to FF
16 16
(Low-order address)
WO
(3, 4)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
(2, 3)
WO
pins are set to
OUT
12. Timer