Resolution Select Function; Sample And Hold; Power Consumption Reducing Function - Renesas M16C FAMILY series Hardware Manual

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15.2 Resolution Select Function

The BITS bit in the ADCON1 register determines the resolution. When the BITS bit is set to "1" (10-bit
precision), the A/D conversion result is stored into bits 0 to 9 in the ADi register (i=0 to 7). When the BITS
bit is set to "0" (8-bit precision), the A/D conversion result is stored into bits 0 to 7 in the ADi register.

15.3 Sample and Hold

When the SMP bit in the ADCON 2 register is set to "1" (with the sample and hold function), A/D conver-
sion rate per pin increases to 28 φAD cycles for 8-bit resolution or 33 φAD cycles for 10-bit resolution. The
sample and hold function is available in one-shot mode, repeat mode, single sweep mode, repeat sweep
mode 0 and repeat sweep mode 1. In these modes, start A/D conversion after selecting whether the
sample and hold circuit is to be used or not. In simultaneous sample sweep mode, delayed trigger mode
0 or delayed trigger mode , set to use the Sample and Hold function before starting A/D conversion.

15.4 Power Consumption Reducing Function

When the A/D converter is not used, the VCUT bit in the ADCON1 register isolates the resistor ladder of
the A/D converter from the reference voltage input pin (V
off any current flow into the resistor ladder from the V
When using the A/D converter, set the VCUT bit to "1" (Vref connected) before setting the ADST bit in the
ADCON0 register to "1" (A/D conversion started). Do not set the ADST bit and VCUT bit to "1" simulta-
neously, nor set the VCUT bit to "0" (Vref unconnected) during A/D conversion.
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
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f o 3 8 5
). Power consumption is reduced by shutting
REF
pin.
REF
15. A/D Converter