Renesas M16C FAMILY series Hardware Manual page 127

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Timer Ai Mode Register (i=2 to 4)
(When using two-phase pulse signal processing)
b6 b5 b4 b3
0 1 0
NOTES:
1. TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in
normal processing mode and x4 processing mode, respectively.
2. If two-phase pulse signal processing is desired, following register settings are required:
• Set the TAiP bit in the UDF register to "1" (two-phase pulse signal processing function enabled).
• Set the TAiTGH and TAiTGL bits in the TRGSR register to '00
• Set the port direction bits for TAi
Figure 12.9 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse
signal processing with timer A2, A3 or A4)
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Symbol
b2 b1 b0
TA2MR to TA4MR
0 0 1
Bit Symbol
TMOD0
Operation mode select bit
TMOD1
MR0
To use two-phase pulse signal processing, set this bit to "0".
MR1
To use two-phase pulse signal processing, set this bit to "0".
MR2
To use two-phase pulse signal processing, set this bit to "1".
MR3
To use two-phase pulse signal processing, set this bit to "0".
Count operation type
TCK0
select bit
Two-phase pulse signal
TCK1
processing operation
select bit
and TAi
IN
page 107
f o 3 8 5
Address
0398 to 039A
16 16
Bit Name
b1 b0
0 1 : Event counter mode
0 : Reload type
1 : Free-run type
0 : Normal processing operation
1 : Multiply-by-4 processing operation
(1)(2)
' (TAiIN pin input).
2
to "0" (input mode).
OUT
After Reset
00
16
Function
12. Timer
RW
RW
RW
RW
RW
RW
RW
RW
RW