Renesas M16C FAMILY series Hardware Manual page 188

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
No reverse
RxD data
RxD2
reverse circuit
Reverse
1SP
STPS=0
SP
STPS=1
2SP
STPS=1
2SP
SP SP
STPS=0
1SP
Figure 14.3 Block Diagram of UART2 Transmit/Receive Unit
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
IOPOL=0
IOPOL=1
PAR
disabled
Clock
synchronous
PRYE=0 type
SP PAR
PRYE=1
PAR UART
enabled
0 0 0 0 0 0
PAR
enabled
UART
PRYE=1
PAR
PRYE=0 Clock
synchronous
type
PAR
disabled
0
page 168
f o 3 8 5
Clock
synchronous type
UART
(7 bits)
UART
UART(7 bits)
(8 bits)
Clock
UART
synchronous type
(9 bits)
UART
(8 bits)
UART
(9 bits)
0
D D D D
8 7 6 5
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D D D
D
7 6 5
8
UART
(8 bits)
UART
(9 bits)
UART
Clock
(9 bits)
synchronous type
UART
UART(7 bits)
(7 bits)
UART
(8 bits)
Clock
synchronous type
Error signal output
U2ERE disable
=0
Error signal
output circuit
U2ERE
Error signal output
=1
enable
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bits in the U2MR register
U2ERE : Bits in the U2C1 register
UARTi receive register
D D D D D
4 3 2 1 0
Address 037E
Address 037F
D D D D D
UART2 transmit
4 3 2 1 0
buffer register
Address 037A
Address 037B
UARTi transmit register
No reverse
IOPOL
=0
TxD data
reverse circuit
IOPOL
Reverse
=1
SP: Stop bit
PAR: Parity bit
14.Serial I/O
UART2 receive
buffer register
16
16
16
16
TxD2