Renesas M16C FAMILY series Hardware Manual page 59

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Low voltage detection circuit
VC27
V +
CC Noise
rejection
Vref
-
(Rejection wide:200 ns)
WAIT instruction(wait mode)
Watchdog timer block
Figure 5.8 Low Voltage Detection Interrupt Generation Block
VCC
VC13 bit
Output of the digital filter
D42 bit
Low voltage detection
interrupt signal
NOTES:
1. D40 bit in the D4INT register is set to "1"(low voltage detection interrupt enabled).
2. Output of the digital filter shown in Figure 5.8.
Figure 5.9 Low voltage Detection Interrupt Generation Circuit Operation Example
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Low voltage detection interrupt generation circuit
D4INT clock(the
1/8 1/2
clock with which it
operates also in
wait mode)
VC13
Low voltage detection
signal
"H" when VC27 bit= 0
(disabled)
CM10
CM02
D43
Watchdog timer
This bit is set to "0"(not detected) by writing a "0" by program.
underflow signal
sampling
(2)
page 39
f o 3 8 5
DF1, DF0
00
2
D42 bit is set to "0"(not detected) by
01
2
writing a "0" in a program. VC27 bit
10
2
is set to "0" (low voltage detection
11
2
circuit disabled), the D42 bit is set to
1/2 1/2
"0".
D42
Noise rejection Digital
circuit
filter
D41
sampling
No low voltage detection interrupt signals are
generated when the D42 bit is "1".
Set to "0" by
program
detected)
Watchdog
timer interrupt
signal
Low voltage
detection
interrupt signal
Oscillation stop,
re-oscillation
detection
interrupt signal
D40
sampling sampling
Set to "0" by a
program
(not (not
detected)
5. Reset
Non-maskable
interrupt signal