Renesas M16C FAMILY series Hardware Manual page 207

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count
source
"1"
UiC1 register
RE bit
"0"
RxDi
Transfer clock
"1"
UiC1 register
RI bit
"0"
"H"
RTSi
"L"
"1"
SiRIC register
IR bit
"0"
The above timing diagram applies to the case where the register bits are set as follows:
• Set the PRYE bit in the UiMR register to "0"(parity disabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTSi/RTSi enabled), the CRS bit to "1" (RTSi selected)
i = 0 to 2
Figure 14.17 Receive Operation
14.1.2.1 Bit Rates
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.
Table 14.9 lists example of bit rate and settings.
Table 14.9 Example of Bit Rates and Settings
Bit Rate Count Source
(bps) of BRG
1200
2400
4800
9600
14400
19200
28800
31250
38400
51200
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Start
bit
Sampled "L"
Reception triggered when transfer clock
is generated by falling edge of start bit
Cleared to "0" when interrupt request is accepted, or cleared to "0" by program
Peripheral Function Clock : 16MHz
Set Value of BRG : n Actual Time (bps) Set Value of BRG : n Actual Time (bps)
f8 103(67h)
f8 51(33h)
f8 25(19h)
f1 103(67h)
f1 68(44h)
f1 51(33h)
f1 34(22h)
f1 31(1Fh)
f1 25(19h)
f1 19(13h)
page 187
f o 3 8 5
D D
D
1 7
0
Receive data taken in
Transferred from UARTi receive
register to UiRB register
Peripheral Function Clock : 20MHz
1202 129(81h)
2404 64(40h)
4808 32(20h)
9615 129(81h)
14493 86(56h)
19231 64(40h)
28571 42(2Ah)
31250 39(27h)
38462 32(20h)
50000 24(18h)
14. Serial I/O
Stop bit
Read out from
UiRB register
1202
2404
4735
9615
14368
19231
29070
31250
37879
50000