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14.1.1.1 Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,
follow the procedures below.
•Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to "0" (reception disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to "000
(3) Set the SMD2 to SMD0 bits in the UiMR register to "001
(4) Set the RE bit in the UiC1 register to "1" (reception enabled)
•Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register to "000
(2) Set the SMD2 to SMD0 bits in the UiMR register to "001
(3) "1" is written to TE bit in the UiC1 register (reception enabled), regardless to the TE bit.
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" (Serial I/O disabled)
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14. Serial I/O