Renesas M16C FAMILY series Hardware Manual page 310

16-bit single-chip microcomputer
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M
1
6
C
2 /
8
G
o r
u
p
(
M
1
6
C
Port Pi Register (i=0 to 3, 6 to 8 and 10)
b7
b6
b5
b4
b3
b2
NOTES:
1. Set the PACR register.
In 80-/85-pin package, set PACR2, PACR1, PACR0 to "011
In 64-pin package, set PACR2, PACR1, PACR0 to "010
Port P9 Register
b7
b6
b5
b4
b3
b2
NOTES:
1. Set the PACR register.
In 80-/85- pin package, set PACR2, PACR1, PACR0 to "011
In 64-pin package, set PACR2, PACR1, PACR0 to "010
2. Nothing is assigned. In an attempt to write t o this bit, write "0".
The value if read turns out to be "0".
Figure 17.7 P0 to P3 and P6 to P10 Registers
R
e
. v
2
0 .
0
J
a
. n
3
, 1
2
0
0
7
R
E
J
0
9
B
0
0
4
7
0 -
2
0
0
2 /
, 8
M
1
6
C
2 /
8
) B
Symbol
Address
P0 to P3
03E0
b1
b0
P6 to P8
03EC
P10
03F4
Bit Symbol
Pi_0
Port Pi
Pi_1
Port Pi
Pi_2
Port Pi
Pi_3
Port Pi
Pi_4
Port Pi
Pi_5
Port Pi
Pi_6
Port Pi
Pi_7
Port Pi
(1)
b1
b0
Symbol
Address
P9
03F1
Bit Symbol
P9_0
Port P9
P9_1
Port P9
P9_2
Port P9
P9_3
Port P9
(b4)
Nothing is assigned
P9_5
Port P9
P9_6
Port P9
P9_7
Port P9
page 290
f o
3
8
5
(1)
, 03E1
, 03E4
, 03E5
16
16
16
, 03ED
, 03F0
16
16
16
16
Bit Name
bit
The pin level on any I/O port which is
0
set for input mode can be read by
bit
1
reading the corresponding bit in this
bit
2
register.
The pin level on any I/O port which is
bit
3
set for output mode can be controlled
bit
4
by writing to the corresponding bit in
this register
bit
5
0 : "L" level
bit
6
1 : "H" level
bit
(i = 0 to 3, 6 to 8 and 10)
7
"
2
"
2
After Reset
Indeterminate
16
Bit Name
bit
0
The pin level on any I/O port which is
bit
set for input mode can be read by
1
reading the corresponding bit in this
bit
2
register.
bit
3
The pin level on any I/O port which is
set for output mode can be controlled
(2)
by writing to the corresponding bit in
bit
5
this register (except for P8
bit
0 : "L" level
6
1 : "H" level
bit
7
"
2
"
2
17. Programmable I/O Ports
After Reset
Indeterminate
16
Indeterminate
Indeterminate
Function
(1)
Function
)
5
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
-
RW
RW
RW

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