M
1
6
C
2 /
8
G
o r
u
p
(
M
1
6
C
Table 14.12 Registers to Be Used and Settings in I
Register
Bit
U2SMR4 STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
NOTES:
1: Not all bits in the register are described above. Set those bits to "0" when writing to the registers in I
R
e
. v
2
0 .
0
J
a
. n
3
, 1
2
0
0
7
R
E
J
0
9
B
0
0
4
7
0 -
2
0
0
2 /
, 8
M
1
6
C
2 /
8
) B
Master
Set this bit to "1" to generate start
condition
Set this bit to "1" to generate restart
condition
Set this bit to "1" to generate stop
condition
Set this bit to "1" to output each condition Set to "0"
Select ACK or NACK
Set this bit to "1" to output ACK data
Set this bit to "1" to have SCL
stopped when stop condition is detected
Set to "0"
page 194
f o
3
8
5
2
C bus Mode (2) (Continued)
Function
Set to "0"
Set to "0"
Set to "0"
Select ACK or NACK
Set this bit to "1" to output ACK data
output
Set to "0"
2
Set this bit to "1" to set the SCL
hold at the falling edge of the 9th bit of
clock
14. Serial I/O
Slave
to "L"
2
2
C bus mode.