Renesas M16C FAMILY series Hardware Manual page 141

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Timer Bi Mode Register (i= 0 to 1)
b7 b6 b5
NOTE:
1. When this bit is used in delayed trigger mode 0, set the same count source to the timer B0 and timer B1.
Figure 12.23 TBiMR Register in A/D Trigger Mode
Timer B2 special mode register
b7 b6 b5
0 0
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this
bit to "0" (timer B2 underflow).
3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), set the PD8_5
bit to "0" (= input mode).
4. Associated pins are U(P8
to the SD pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-
impedance state. If a low-level ("L") signal is applied to the SD pin, three-phase motor control timer output will
be disabled (INV03=0). At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become
programmable I/O ports. When the IVPCR1 bit is set to 1, pins U, U, V, V, W, and W are placed in a high-
impedance state regardless of which function of those pins is used.
5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1" (A/D trigger mode).
6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]),
set the INV02 bit to "1" (three-phase motor control timer function).
7. Refer to "17.6 Digital Debounce Function" for the SD input
Figure 12.24 TB2SC Register in A/D Trigger Mode
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
b4 b3 b2 b1 b0
Symbol
TB0MR to TB1MR
0 0
Bit Symbol
TMOD0
Operation mode select bit
TMOD1
MR0
Invalid in A/D trigger mode
Either "0" or "1" is enabled
MR1
TB0MR register
Set to "0" in A/D trigger mode
MR2
TB1MR register
Nothing is assigned. When write, set to "0".
When read, the content is indeterminate
When write in A/D trigger mode, set to "0". When read in A/D
MR3
trigger mode, its content is indeterminate.
TCK0
Count source select bit
TCK1
(1)
b4 b3 b2 b1 b0
Symbol
1 1
TB2SC
Bit Symbol
PWCON Timer B2 Reload Timing
Switch Bit
Three-Phase Output Port
IVPCR1
SD Control Bit 1
Timer B0 Operation Mode
TB0EN
Select Bit
Timer B1 Operation Mode
TB1EN
Select Bit
TB2SEL Trigger Select Bit
Reserved bits
(b6-b5)
Nothing is assigned. When write, set to "0".
(b7)
When read, the content is "0"
), U(P8 ), V(P7
0 1
page 121
f o 3 8 5
Address
039B to 039C
16 16
Bit Name
b1 b0
0 0 : Timer mode or A/D trigger mode
b7 b6
0 0 : f or f
1
(1)
0 1 : f
8
1 0 : f
32
1 1 : f
C32
After Reset
Address
039E X0000000
16 2
Bit Name
0 : Timer B2 underflow
(2)
1 : Timer A output at odd-numbered
0 : Three-phase output forcible cutoff
by SD pin input (high impedance)
disabled
(3, 4, 7)
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
0 : Other than A/D trigger mode
1 : A/D trigger mode
0 : Other than A/D trigger mode
1 : A/D trigger mode
0 : TB2 interrupt
(6)
1 : Underflow of TB2 interrupt generation
frequency setting counter [ICTB2]
Set to "0"
), V(P7 ), W(P7 ), W(P7 ). When a high-level ("H") signal is applied
2 3 4 5
After Reset
00XX0000
2
Function RW
RW
RW
RW
RW
RW
RO
RW
2
RW
Function
(5)
(5)
12. Timer
RW
RW
RW
RW
RW
RW
RW