Renesas M16C FAMILY series Hardware Manual page 301

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
(2) Generation of RESTART condition
In order to generate a RESTART condition after 1-byte data transfer, write "E0
enter START condition standby mode and leave the SDA
by setting the S00 register after inserting a sufficient software wait until the SDA
("H") signal. Figure 16.24 shows the RESTART condition generation timing.
8 clock
S
CL
S
DA
S1I writing signal
( START condition setting standby)
S0I writing signal
(START condition trigger generation)
Figure 16.24 The time of generation of RESTART condition
(3) Iimitation of CPU clock
When the CM07 bit in the CM0 register is set to "1" (subclock), each register of the I
circuit cannot be read or written. Read or write data when the CM07 bit is set to "0" (main clock, PLL
clock, or on-chip oscillator clock).
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
ACK
clock
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f o 3 8 5
16. MULTI-MASTER I
16
open. Generate a START condition trigger
MM
MM
Insert software wait
2
C bus INTERFACE
" to the S10 register,
outputs a high-level
2
C bus interface