Renesas M16C FAMILY series Hardware Manual page 216

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
(1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay)
1st 2nd
bit
SCL2
D
7
SDA2
(2) When the IICM2 bit is set to "0" and the CKPH bit is set to "1" (clock delay)
1st
bit
SCL2
D
7
SDA2
(3) When the IICM2 bit is set to "1" (UART transmit or receive interrupt) and the CKPH bit is set to "0"
1st 2nd
bit
SCL2
D
7
SDA2
(4) When the IICM2 bit is set to "1" and the CKPH bit is set to "1"
1st 2nd
bit
SCL2
D
7
SDA2
The above timing applies to the following setting :
• The CKDIR bit in the U2MR register is set to "1" (slave)
Figure 14.23 Transfer to U2RB Register and Interrupt Timing
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
3rd 4th 5th 6th
bit bit bit bit
D D D D
6 5 4 3
2nd 3rd 4th 5th
bit bit bit bit
D D D D
6 5 4 3
3rd 4th 5th 6th
bit bit bit bit
D D D D
6 5 4 3
Data is transferred to the U2RB register
3rd 4th 5th 6th
bit bit bit bit
D D D D
6 5 4 3
Data is transferred to the U2RB register
b15 b9 b8
D
••• 0
Contents of the U2RB register
page 196
f o 3 8 5
7th 8th 9th
bit bit bit bit
D D D D (ACK or NACK)
2 1 0 8
ACK interrupt (DMA
request) or NACK interrupt
Data is transferred to the U2RB register
6th 7th 8th 9th
bit bit bit bit
D D D D (ACK or NACK)
2 1 0 8
ACK interrupt (DMA
request) or NACK interrupt
Data is transferred to the U2RB register
7th 8th 9th
bit bit bit bit
D (ACK or NACK)
D D D
8
2 1 0
Receive interrupt
Transmit interrupt
(DMA request)
b15
•••
7th 8th 9th
bit bit bit bit
D D D D (ACK or NACK)
2 1 0 8
Receive interrupt
Transmit interrupt
(DMA request)
Data is transferred to the U2RB register
b7 b0 b15
D D D D D D D
7 6 5 4 3 2 1 •••
b15 b9 b8 b7
D D D D
••• 8 7 6 5
Contents of the U2RB register
b15 b9 b8 b7
D D D D
•••
8 7 6 5
Contents of the U2RB register
b9 b8 b7 b0
D D D D D D D D
0 7 6 5 4 3 2 1
Contents of the U2RB register
b9 b8 b7 b0
D D D D D D D D D
8 7 6 5 4 3 2 1 0
Contents of the U2RB register
14. Serial I/O
b0
D D D D D
4 3 2 1 0
b0
D D D D D
4 3 2 1 0