Renesas M16C FAMILY series Hardware Manual page 194
16-bit single-chip microcomputer
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Also See for M16C FAMILY series:
- User manual (380 pages) ,
- Hardware manual (257 pages) ,
- Hardware manual (468 pages)
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M
1
6
C
2 /
8
G
o r
u
p
(
M
1
6
C
UART2 Special Mode Register 3
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
1. The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I
2
I
C bus mode, set these bits to "000
2. The amount of delay varies with the load on SCL2 and SDA2 pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
UART2 Special Mode Register 4
b7 b6 b5 b4 b3 b2 b1 b0
NOTE:
1. Set to "0" when each condition is generated.
Figure 14.9 U2SMR3 and U2SMR4 Registers
R
e
. v
2
0 .
0
J
a
. n
3
, 1
2
0
0
7
R
E
J
0
9
B
0
0
4
7
0 -
2
0
0
2 /
, 8
M
1
6
C
2 /
8
) B
Symbol
U2SMR3
Bit
Bit Name
Symbol
Nothing is assigned.
(b0)
When write, set "0". When read, its content is indeterminate.
CKPH
Clock phase set bit
Nothing is assigned.
(b2)
When write, set "0". When read, its content is indeterminate.
NODC
Clock output select bit
Nothing is assigned.
(b4)
When write, set "0". When read, its content is indeterminate.
DL0
SDA digital delay
setup bit
(1, 2)
DL1
DL2
" ( UART mode transfer data 9 bits long).
2
Symbol
U2SMR4
Bit Symbol
Start condition
STAREQ
generate bit
Restart condition
RSTAREQ
generate bit
Stop condition
STPREQ
STSPSEL
SCL
ACK data bit
ACKD
ACK data output
ACKC
SCL
SCLHI
SCL
SWC9
page 174
f o
3
8
5
Address
After Reset
0375
000X0X0X
16
0 : Without clock delay
1 : With clock delay
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
b7 b6 b5
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
Address
After Reset
0374
00
16
16
Bit Name
0: Clear
(1)
1: Start
0: Clear
(1)
1: Start
0: Clear
1: Start
0: Start and stop conditions not output
, SDA
output
2
2
1: Start and stop conditions output
0: ACK
1: NACK
0: Serial I/O data output
1: ACK data output
0: Disabled
output stop
2
1: Enabled
0: SCL
"L" hold disabled
2
wait bit 3
2
1: SCL
"L" hold enabled
2
2
Function
2
C bus mode. In other than
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
14.Serial I/O
RW
RW
RW
RW
RW
RW
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